diff options
author | Russell King <rmk+kernel@arm.linux.org.uk> | 2011-08-27 17:39:09 -0400 |
---|---|---|
committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2011-09-20 18:33:38 -0400 |
commit | de8e71ca4f2e17329f6718ae88d5c8336cb249ee (patch) | |
tree | cec0f26c5f4c9efd601edc1ac716aed168f65e1f /arch/arm/mm/proc-arm926.S | |
parent | e8ce0eb5e2254b85415e4b58e73f24a5d13846a1 (diff) |
ARM: pm: only use preallocated page table during resume
Only use the preallocated page table during the resume, not while
suspending. This avoids the overhead of having to switch unnecessarily
to the resume page table in the suspend path.
Tested-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Tested-by: Shawn Guo <shawn.guo@linaro.org>
Tested-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mm/proc-arm926.S')
-rw-r--r-- | arch/arm/mm/proc-arm926.S | 17 |
1 files changed, 8 insertions, 9 deletions
diff --git a/arch/arm/mm/proc-arm926.S b/arch/arm/mm/proc-arm926.S index 48add848b997..9f8fd91f918a 100644 --- a/arch/arm/mm/proc-arm926.S +++ b/arch/arm/mm/proc-arm926.S | |||
@@ -394,27 +394,26 @@ ENTRY(cpu_arm926_set_pte_ext) | |||
394 | 394 | ||
395 | /* Suspend/resume support: taken from arch/arm/plat-s3c24xx/sleep.S */ | 395 | /* Suspend/resume support: taken from arch/arm/plat-s3c24xx/sleep.S */ |
396 | .globl cpu_arm926_suspend_size | 396 | .globl cpu_arm926_suspend_size |
397 | .equ cpu_arm926_suspend_size, 4 * 4 | 397 | .equ cpu_arm926_suspend_size, 4 * 3 |
398 | #ifdef CONFIG_PM_SLEEP | 398 | #ifdef CONFIG_PM_SLEEP |
399 | ENTRY(cpu_arm926_do_suspend) | 399 | ENTRY(cpu_arm926_do_suspend) |
400 | stmfd sp!, {r4 - r7, lr} | 400 | stmfd sp!, {r4 - r6, lr} |
401 | mrc p15, 0, r4, c13, c0, 0 @ PID | 401 | mrc p15, 0, r4, c13, c0, 0 @ PID |
402 | mrc p15, 0, r5, c3, c0, 0 @ Domain ID | 402 | mrc p15, 0, r5, c3, c0, 0 @ Domain ID |
403 | mrc p15, 0, r6, c2, c0, 0 @ TTB address | 403 | mrc p15, 0, r6, c1, c0, 0 @ Control register |
404 | mrc p15, 0, r7, c1, c0, 0 @ Control register | 404 | stmia r0, {r4 - r6} |
405 | stmia r0, {r4 - r7} | 405 | ldmfd sp!, {r4 - r6, pc} |
406 | ldmfd sp!, {r4 - r7, pc} | ||
407 | ENDPROC(cpu_arm926_do_suspend) | 406 | ENDPROC(cpu_arm926_do_suspend) |
408 | 407 | ||
409 | ENTRY(cpu_arm926_do_resume) | 408 | ENTRY(cpu_arm926_do_resume) |
410 | mov ip, #0 | 409 | mov ip, #0 |
411 | mcr p15, 0, ip, c8, c7, 0 @ invalidate I+D TLBs | 410 | mcr p15, 0, ip, c8, c7, 0 @ invalidate I+D TLBs |
412 | mcr p15, 0, ip, c7, c7, 0 @ invalidate I+D caches | 411 | mcr p15, 0, ip, c7, c7, 0 @ invalidate I+D caches |
413 | ldmia r0, {r4 - r7} | 412 | ldmia r0, {r4 - r6} |
414 | mcr p15, 0, r4, c13, c0, 0 @ PID | 413 | mcr p15, 0, r4, c13, c0, 0 @ PID |
415 | mcr p15, 0, r5, c3, c0, 0 @ Domain ID | 414 | mcr p15, 0, r5, c3, c0, 0 @ Domain ID |
416 | mcr p15, 0, r6, c2, c0, 0 @ TTB address | 415 | mcr p15, 0, r1, c2, c0, 0 @ TTB address |
417 | mov r0, r7 @ control register | 416 | mov r0, r6 @ control register |
418 | b cpu_resume_mmu | 417 | b cpu_resume_mmu |
419 | ENDPROC(cpu_arm926_do_resume) | 418 | ENDPROC(cpu_arm926_do_resume) |
420 | #endif | 419 | #endif |