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authorRussell King <rmk+kernel@arm.linux.org.uk>2011-02-06 10:48:39 -0500
committerRussell King <rmk+kernel@arm.linux.org.uk>2011-02-22 12:11:23 -0500
commitf6b0fa02e8b0708d17d631afce456524eadf87ff (patch)
tree900fcd2149a03ba229bb29e982d3d6a5f3d3fcfc /arch/arm/mm/proc-arm926.S
parent753790e713d80b50b867fa1ed32ec0eb5e82ae8e (diff)
ARM: pm: add generic CPU suspend/resume support
This adds core support for saving and restoring CPU coprocessor registers for suspend/resume support. This contains support for suspend with ARM920, ARM926, SA11x0, PXA25x, PXA27x, PXA3xx, V6 and V7 CPUs. Tested on Assabet and Tegra 2. Tested-by: Colin Cross <ccross@android.com> Tested-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mm/proc-arm926.S')
-rw-r--r--arch/arm/mm/proc-arm926.S37
1 files changed, 37 insertions, 0 deletions
diff --git a/arch/arm/mm/proc-arm926.S b/arch/arm/mm/proc-arm926.S
index 42eb4315740b..6a4bdb2c94a7 100644
--- a/arch/arm/mm/proc-arm926.S
+++ b/arch/arm/mm/proc-arm926.S
@@ -401,6 +401,40 @@ ENTRY(cpu_arm926_set_pte_ext)
401#endif 401#endif
402 mov pc, lr 402 mov pc, lr
403 403
404/* Suspend/resume support: taken from arch/arm/plat-s3c24xx/sleep.S */
405.globl cpu_arm926_suspend_size
406.equ cpu_arm926_suspend_size, 4 * 3
407#ifdef CONFIG_PM
408ENTRY(cpu_arm926_do_suspend)
409 stmfd sp!, {r4 - r7, lr}
410 mrc p15, 0, r4, c13, c0, 0 @ PID
411 mrc p15, 0, r5, c3, c0, 0 @ Domain ID
412 mrc p15, 0, r6, c2, c0, 0 @ TTB address
413 mrc p15, 0, r7, c1, c0, 0 @ Control register
414 stmia r0, {r4 - r7}
415 ldmfd sp!, {r4 - r7, pc}
416ENDPROC(cpu_arm926_do_suspend)
417
418ENTRY(cpu_arm926_do_resume)
419 mov ip, #0
420 mcr p15, 0, ip, c8, c7, 0 @ invalidate I+D TLBs
421 mcr p15, 0, ip, c7, c7, 0 @ invalidate I+D caches
422 ldmia r0, {r4 - r7}
423 mcr p15, 0, r4, c13, c0, 0 @ PID
424 mcr p15, 0, r5, c3, c0, 0 @ Domain ID
425 mcr p15, 0, r6, c2, c0, 0 @ TTB address
426 mov r0, r7 @ control register
427 mov r2, r6, lsr #14 @ get TTB0 base
428 mov r2, r2, lsl #14
429 ldr r3, =PMD_TYPE_SECT | PMD_SECT_BUFFERABLE | \
430 PMD_SECT_CACHEABLE | PMD_BIT4 | PMD_SECT_AP_WRITE
431 b cpu_resume_mmu
432ENDPROC(cpu_arm926_do_resume)
433#else
434#define cpu_arm926_do_suspend 0
435#define cpu_arm926_do_resume 0
436#endif
437
404 __CPUINIT 438 __CPUINIT
405 439
406 .type __arm926_setup, #function 440 .type __arm926_setup, #function
@@ -456,6 +490,9 @@ arm926_processor_functions:
456 .word cpu_arm926_dcache_clean_area 490 .word cpu_arm926_dcache_clean_area
457 .word cpu_arm926_switch_mm 491 .word cpu_arm926_switch_mm
458 .word cpu_arm926_set_pte_ext 492 .word cpu_arm926_set_pte_ext
493 .word cpu_arm926_suspend_size
494 .word cpu_arm926_do_suspend
495 .word cpu_arm926_do_resume
459 .size arm926_processor_functions, . - arm926_processor_functions 496 .size arm926_processor_functions, . - arm926_processor_functions
460 497
461 .section ".rodata" 498 .section ".rodata"