diff options
author | Lennert Buytenhek <buytenh@wantstofly.org> | 2008-05-10 16:05:31 -0400 |
---|---|---|
committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2008-05-17 17:55:14 -0400 |
commit | b3a8b751c1c2997653c6bf2b5d10467c39f3cc6e (patch) | |
tree | 3b41e1ba606f9f1fb1aa08d4c66b873c7443fb94 /arch/arm/mm/proc-arm925.S | |
parent | db2c4392907524fa376ffbd04f5781d6394e2666 (diff) |
[ARM] 5034/1: fix arm{925,926,940,946} dma_flush_range() in WT mode
The CPU's dma_flush_range() operation needs to clean+invalidate the
given memory area if the cache is in writeback mode, or do just the
invalidate part if the cache is in writethrough mode, but the current
proc-arm{925,926,940,946} (incorrectly) do a cache clean in the
latter case. This patch fixes that.
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mm/proc-arm925.S')
-rw-r--r-- | arch/arm/mm/proc-arm925.S | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mm/proc-arm925.S b/arch/arm/mm/proc-arm925.S index 065087afb772..d045812f3399 100644 --- a/arch/arm/mm/proc-arm925.S +++ b/arch/arm/mm/proc-arm925.S | |||
@@ -332,7 +332,7 @@ ENTRY(arm925_dma_flush_range) | |||
332 | #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH | 332 | #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH |
333 | mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry | 333 | mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry |
334 | #else | 334 | #else |
335 | mcr p15, 0, r0, c7, c10, 1 @ clean D entry | 335 | mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry |
336 | #endif | 336 | #endif |
337 | add r0, r0, #CACHE_DLINESIZE | 337 | add r0, r0, #CACHE_DLINESIZE |
338 | cmp r0, r1 | 338 | cmp r0, r1 |