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authorLinus Torvalds <torvalds@g5.osdl.org>2006-06-28 19:20:49 -0400
committerLinus Torvalds <torvalds@g5.osdl.org>2006-06-28 19:20:49 -0400
commit27d68a36c4f1ca2fc6be82620843493462c08c51 (patch)
treea06b451e19c25a77595c918ca81bbb30f0ec9ebf /arch/arm/mm/proc-arm925.S
parent76a22271fd14e3fe7660f8646db12f0780fa4fd2 (diff)
parent583e7f5d36547f0d84caf71d43b71f0530a47766 (diff)
Merge branch 'nommu' of master.kernel.org:/home/rmk/linux-2.6-arm
* 'nommu' of master.kernel.org:/home/rmk/linux-2.6-arm: [ARM] nommu: backtrace code must not reference a discarded section [ARM] nommu: Initial uCLinux support for MMU-based CPUs [ARM] nommu: prevent Xscale-based machines being selected [ARM] nommu: export flush_dcache_page() [ARM] nommu: remove fault-armv, mmap and mm-armv files from nommu build [ARM] Remove TABLE_SIZE, and several unused function prototypes [ARM] nommu: Provide a simple flush_dcache_page implementation [ARM] nommu: add arch/arm/Kconfig-nommu to Kconfig files [ARM] nommu: add stubs for ioremap and friends [ARM] nommu: avoid selecting TLB and CPU specific copy code [ARM] nommu: uaccess tweaks [ARM] nommu: adjust headers for !MMU ARM systems [ARM] nommu: we need the TLS register emulation for nommu mode
Diffstat (limited to 'arch/arm/mm/proc-arm925.S')
-rw-r--r--arch/arm/mm/proc-arm925.S10
1 files changed, 10 insertions, 0 deletions
diff --git a/arch/arm/mm/proc-arm925.S b/arch/arm/mm/proc-arm925.S
index 224ce226a01b..8d47c9f3f931 100644
--- a/arch/arm/mm/proc-arm925.S
+++ b/arch/arm/mm/proc-arm925.S
@@ -9,6 +9,8 @@
9 * Update for Linux-2.6 and cache flush improvements 9 * Update for Linux-2.6 and cache flush improvements
10 * Copyright (C) 2004 Nokia Corporation by Tony Lindgren <tony@atomide.com> 10 * Copyright (C) 2004 Nokia Corporation by Tony Lindgren <tony@atomide.com>
11 * 11 *
12 * hacked for non-paged-MM by Hyok S. Choi, 2004.
13 *
12 * This program is free software; you can redistribute it and/or modify 14 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by 15 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or 16 * the Free Software Foundation; either version 2 of the License, or
@@ -122,7 +124,9 @@ ENTRY(cpu_arm925_reset)
122 mov ip, #0 124 mov ip, #0
123 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 125 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
124 mcr p15, 0, ip, c7, c10, 4 @ drain WB 126 mcr p15, 0, ip, c7, c10, 4 @ drain WB
127#ifdef CONFIG_MMU
125 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 128 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
129#endif
126 mrc p15, 0, ip, c1, c0, 0 @ ctrl register 130 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
127 bic ip, ip, #0x000f @ ............wcam 131 bic ip, ip, #0x000f @ ............wcam
128 bic ip, ip, #0x1100 @ ...i...s........ 132 bic ip, ip, #0x1100 @ ...i...s........
@@ -369,6 +373,7 @@ ENTRY(cpu_arm925_dcache_clean_area)
369 */ 373 */
370 .align 5 374 .align 5
371ENTRY(cpu_arm925_switch_mm) 375ENTRY(cpu_arm925_switch_mm)
376#ifdef CONFIG_MMU
372 mov ip, #0 377 mov ip, #0
373#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH 378#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
374 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache 379 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
@@ -383,6 +388,7 @@ ENTRY(cpu_arm925_switch_mm)
383 mcr p15, 0, ip, c7, c10, 4 @ drain WB 388 mcr p15, 0, ip, c7, c10, 4 @ drain WB
384 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer 389 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
385 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 390 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
391#endif
386 mov pc, lr 392 mov pc, lr
387 393
388/* 394/*
@@ -392,6 +398,7 @@ ENTRY(cpu_arm925_switch_mm)
392 */ 398 */
393 .align 5 399 .align 5
394ENTRY(cpu_arm925_set_pte) 400ENTRY(cpu_arm925_set_pte)
401#ifdef CONFIG_MMU
395 str r1, [r0], #-2048 @ linux version 402 str r1, [r0], #-2048 @ linux version
396 403
397 eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY 404 eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
@@ -420,6 +427,7 @@ ENTRY(cpu_arm925_set_pte)
420 mcr p15, 0, r0, c7, c10, 1 @ clean D entry 427 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
421#endif 428#endif
422 mcr p15, 0, r0, c7, c10, 4 @ drain WB 429 mcr p15, 0, r0, c7, c10, 4 @ drain WB
430#endif /* CONFIG_MMU */
423 mov pc, lr 431 mov pc, lr
424 432
425 __INIT 433 __INIT
@@ -438,7 +446,9 @@ __arm925_setup:
438 mov r0, #0 446 mov r0, #0
439 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4 447 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
440 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4 448 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
449#ifdef CONFIG_MMU
441 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4 450 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
451#endif
442 452
443#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH 453#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
444 mov r0, #4 @ disable write-back on caches explicitly 454 mov r0, #4 @ disable write-back on caches explicitly