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authorHyok S. Choi <hyok.choi@samsung.com>2006-06-28 09:10:01 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2006-06-28 12:59:56 -0400
commitd090dddaba7c8da6401bb259340dce05ca32f564 (patch)
treec35d9e22dc09d40144b4a672962269ff60c9ad07 /arch/arm/mm/proc-arm925.S
parenta4f7e76367f7775ecf534a37b4623c83d9d7ba74 (diff)
[ARM] nommu: Initial uCLinux support for MMU-based CPUs
In noMMU mode, various of functions which are defined in mm/proc-*.S is not valid or needed to be avoided. i.g. switch_mm is not needed, just returns and this makes the I & D caches are valid which shows great improvement of performance including task switching and IPC. Signed-off-by: Hyok S. Choi <hyok.choi@samsung.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mm/proc-arm925.S')
-rw-r--r--arch/arm/mm/proc-arm925.S10
1 files changed, 10 insertions, 0 deletions
diff --git a/arch/arm/mm/proc-arm925.S b/arch/arm/mm/proc-arm925.S
index 224ce226a01b..8d47c9f3f931 100644
--- a/arch/arm/mm/proc-arm925.S
+++ b/arch/arm/mm/proc-arm925.S
@@ -9,6 +9,8 @@
9 * Update for Linux-2.6 and cache flush improvements 9 * Update for Linux-2.6 and cache flush improvements
10 * Copyright (C) 2004 Nokia Corporation by Tony Lindgren <tony@atomide.com> 10 * Copyright (C) 2004 Nokia Corporation by Tony Lindgren <tony@atomide.com>
11 * 11 *
12 * hacked for non-paged-MM by Hyok S. Choi, 2004.
13 *
12 * This program is free software; you can redistribute it and/or modify 14 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by 15 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or 16 * the Free Software Foundation; either version 2 of the License, or
@@ -122,7 +124,9 @@ ENTRY(cpu_arm925_reset)
122 mov ip, #0 124 mov ip, #0
123 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 125 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
124 mcr p15, 0, ip, c7, c10, 4 @ drain WB 126 mcr p15, 0, ip, c7, c10, 4 @ drain WB
127#ifdef CONFIG_MMU
125 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 128 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
129#endif
126 mrc p15, 0, ip, c1, c0, 0 @ ctrl register 130 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
127 bic ip, ip, #0x000f @ ............wcam 131 bic ip, ip, #0x000f @ ............wcam
128 bic ip, ip, #0x1100 @ ...i...s........ 132 bic ip, ip, #0x1100 @ ...i...s........
@@ -369,6 +373,7 @@ ENTRY(cpu_arm925_dcache_clean_area)
369 */ 373 */
370 .align 5 374 .align 5
371ENTRY(cpu_arm925_switch_mm) 375ENTRY(cpu_arm925_switch_mm)
376#ifdef CONFIG_MMU
372 mov ip, #0 377 mov ip, #0
373#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH 378#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
374 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache 379 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
@@ -383,6 +388,7 @@ ENTRY(cpu_arm925_switch_mm)
383 mcr p15, 0, ip, c7, c10, 4 @ drain WB 388 mcr p15, 0, ip, c7, c10, 4 @ drain WB
384 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer 389 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
385 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 390 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
391#endif
386 mov pc, lr 392 mov pc, lr
387 393
388/* 394/*
@@ -392,6 +398,7 @@ ENTRY(cpu_arm925_switch_mm)
392 */ 398 */
393 .align 5 399 .align 5
394ENTRY(cpu_arm925_set_pte) 400ENTRY(cpu_arm925_set_pte)
401#ifdef CONFIG_MMU
395 str r1, [r0], #-2048 @ linux version 402 str r1, [r0], #-2048 @ linux version
396 403
397 eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY 404 eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
@@ -420,6 +427,7 @@ ENTRY(cpu_arm925_set_pte)
420 mcr p15, 0, r0, c7, c10, 1 @ clean D entry 427 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
421#endif 428#endif
422 mcr p15, 0, r0, c7, c10, 4 @ drain WB 429 mcr p15, 0, r0, c7, c10, 4 @ drain WB
430#endif /* CONFIG_MMU */
423 mov pc, lr 431 mov pc, lr
424 432
425 __INIT 433 __INIT
@@ -438,7 +446,9 @@ __arm925_setup:
438 mov r0, #0 446 mov r0, #0
439 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4 447 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
440 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4 448 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
449#ifdef CONFIG_MMU
441 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4 450 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
451#endif
442 452
443#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH 453#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
444 mov r0, #4 @ disable write-back on caches explicitly 454 mov r0, #4 @ disable write-back on caches explicitly