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authorLinus Torvalds <torvalds@g5.osdl.org>2006-07-02 18:04:12 -0400
committerLinus Torvalds <torvalds@g5.osdl.org>2006-07-02 18:04:12 -0400
commita8c4c20dfa8b28a3c99e33c639d9c2ea5657741e (patch)
tree887b64d29b5a46d9ab2ca1267d8a2f05b5845561 /arch/arm/mm/proc-arm922.S
parent168d04b3b4de7723eb73b3cffc9cb75224e0f393 (diff)
parent2dc7667b9d0674db6572723356fe3857031101a4 (diff)
Merge branch 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm
* 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm: (44 commits) [ARM] 3541/2: workaround for PXA27x erratum E7 [ARM] nommu: provide a way for correct control register value selection [ARM] 3705/1: add supersection support to ioremap() [ARM] 3707/1: iwmmxt: use the generic thread notifier infrastructure [ARM] 3706/2: ep93xx: add cirrus logic edb9315a support [ARM] 3704/1: format IOP Kconfig with tabs, create more consistency [ARM] 3703/1: Add help description for ARCH_EP80219 [ARM] 3678/1: MMC: Make OMAP MMC work [ARM] 3677/1: OMAP: Update H2 defconfig [ARM] 3676/1: ARM: OMAP: Fix dmtimers and timer32k to compile on OMAP1 [ARM] Add section support to ioremap [ARM] Fix sa11x0 SDRAM selection [ARM] Set bit 4 on section mappings correctly depending on CPU [ARM] 3666/1: TRIZEPS4 [1/5] core ARM: OMAP: Multiplexing for 24xx GPMC wait pin monitoring ARM: OMAP: Fix SRAM to use MT_MEMORY instead of MT_DEVICE ARM: OMAP: Update dmtimers ARM: OMAP: Make clock variables static ARM: OMAP: Fix GPMC compilation when DEBUG is defined ARM: OMAP: Mux updates for external DMA and GPIO ...
Diffstat (limited to 'arch/arm/mm/proc-arm922.S')
-rw-r--r--arch/arm/mm/proc-arm922.S33
1 files changed, 11 insertions, 22 deletions
diff --git a/arch/arm/mm/proc-arm922.S b/arch/arm/mm/proc-arm922.S
index 1ad464cc7bcb..571f082f0247 100644
--- a/arch/arm/mm/proc-arm922.S
+++ b/arch/arm/mm/proc-arm922.S
@@ -394,11 +394,11 @@ __arm922_setup:
394#ifdef CONFIG_MMU 394#ifdef CONFIG_MMU
395 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4 395 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
396#endif 396#endif
397 adr r5, arm922_crval
398 ldmia r5, {r5, r6}
397 mrc p15, 0, r0, c1, c0 @ get control register v4 399 mrc p15, 0, r0, c1, c0 @ get control register v4
398 ldr r5, arm922_cr1_clear
399 bic r0, r0, r5 400 bic r0, r0, r5
400 ldr r5, arm922_cr1_set 401 orr r0, r0, r6
401 orr r0, r0, r5
402 mov pc, lr 402 mov pc, lr
403 .size __arm922_setup, . - __arm922_setup 403 .size __arm922_setup, . - __arm922_setup
404 404
@@ -408,12 +408,9 @@ __arm922_setup:
408 * ..11 0001 ..11 0101 408 * ..11 0001 ..11 0101
409 * 409 *
410 */ 410 */
411 .type arm922_cr1_clear, #object 411 .type arm922_crval, #object
412 .type arm922_cr1_set, #object 412arm922_crval:
413arm922_cr1_clear: 413 crval clear=0x00003f3f, mmuset=0x00003135, ucset=0x00001130
414 .word 0x3f3f
415arm922_cr1_set:
416 .word 0x3135
417 414
418 __INITDATA 415 __INITDATA
419 416
@@ -447,19 +444,7 @@ cpu_elf_name:
447 444
448 .type cpu_arm922_name, #object 445 .type cpu_arm922_name, #object
449cpu_arm922_name: 446cpu_arm922_name:
450 .ascii "ARM922T" 447 .asciz "ARM922T"
451#ifndef CONFIG_CPU_ICACHE_DISABLE
452 .ascii "i"
453#endif
454#ifndef CONFIG_CPU_DCACHE_DISABLE
455 .ascii "d"
456#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
457 .ascii "(wt)"
458#else
459 .ascii "(wb)"
460#endif
461#endif
462 .ascii "\0"
463 .size cpu_arm922_name, . - cpu_arm922_name 448 .size cpu_arm922_name, . - cpu_arm922_name
464 449
465 .align 450 .align
@@ -476,6 +461,10 @@ __arm922_proc_info:
476 PMD_BIT4 | \ 461 PMD_BIT4 | \
477 PMD_SECT_AP_WRITE | \ 462 PMD_SECT_AP_WRITE | \
478 PMD_SECT_AP_READ 463 PMD_SECT_AP_READ
464 .long PMD_TYPE_SECT | \
465 PMD_BIT4 | \
466 PMD_SECT_AP_WRITE | \
467 PMD_SECT_AP_READ
479 b __arm922_setup 468 b __arm922_setup
480 .long cpu_arch_name 469 .long cpu_arch_name
481 .long cpu_elf_name 470 .long cpu_elf_name