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authorRussell King <rmk@dyn-67.arm.linux.org.uk>2006-06-29 10:09:57 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2006-06-29 10:09:57 -0400
commit22b1908610dd7ff68471cd4fbd383dbdfe5e0ecd (patch)
tree696d910ef791433a6a6bbd30ae841a106ce78a88 /arch/arm/mm/proc-arm922.S
parent264edb35ce5c85749bfdd2942c74b786ea1cde41 (diff)
[ARM] nommu: provide a way for correct control register value selection
Most MMU-based CPUs have a restriction on the setting of the data cache enable and mmu enable bits in the control register, whereby if the data cache is enabled, the MMU must also be enabled. Enabling the data cache without the MMU is an invalid combination. However, there are CPUs where the data cache can be enabled without the MMU. In order to allow these CPUs to take advantage of that, provide a method whereby each proc-*.S file defines the control regsiter value for use with nommu (with the MMU disabled.) Later on, when we add support for enabling the MMU on these devices, we can adjust the "crval" macro to also enable the data cache for nommu. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mm/proc-arm922.S')
-rw-r--r--arch/arm/mm/proc-arm922.S15
1 files changed, 6 insertions, 9 deletions
diff --git a/arch/arm/mm/proc-arm922.S b/arch/arm/mm/proc-arm922.S
index 33dae4929f09..0d237693d0a4 100644
--- a/arch/arm/mm/proc-arm922.S
+++ b/arch/arm/mm/proc-arm922.S
@@ -395,11 +395,11 @@ __arm922_setup:
395#ifdef CONFIG_MMU 395#ifdef CONFIG_MMU
396 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4 396 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
397#endif 397#endif
398 adr r5, arm922_crval
399 ldmia r5, {r5, r6}
398 mrc p15, 0, r0, c1, c0 @ get control register v4 400 mrc p15, 0, r0, c1, c0 @ get control register v4
399 ldr r5, arm922_cr1_clear
400 bic r0, r0, r5 401 bic r0, r0, r5
401 ldr r5, arm922_cr1_set 402 orr r0, r0, r6
402 orr r0, r0, r5
403 mov pc, lr 403 mov pc, lr
404 .size __arm922_setup, . - __arm922_setup 404 .size __arm922_setup, . - __arm922_setup
405 405
@@ -409,12 +409,9 @@ __arm922_setup:
409 * ..11 0001 ..11 0101 409 * ..11 0001 ..11 0101
410 * 410 *
411 */ 411 */
412 .type arm922_cr1_clear, #object 412 .type arm922_crval, #object
413 .type arm922_cr1_set, #object 413arm922_crval:
414arm922_cr1_clear: 414 crval clear=0x00003f3f, mmuset=0x00003135, ucset=0x00001130
415 .word 0x3f3f
416arm922_cr1_set:
417 .word 0x3135
418 415
419 __INITDATA 416 __INITDATA
420 417