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authorLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
committerLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
commit1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 (patch)
tree0bba044c4ce775e45a88a51686b5d9f90697ea9d /arch/arm/mm/proc-arm6_7.S
Linux-2.6.12-rc2v2.6.12-rc2
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
Diffstat (limited to 'arch/arm/mm/proc-arm6_7.S')
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diff --git a/arch/arm/mm/proc-arm6_7.S b/arch/arm/mm/proc-arm6_7.S
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1/*
2 * linux/arch/arm/mm/proc-arm6,7.S
3 *
4 * Copyright (C) 1997-2000 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * These are the low level assembler for performing cache and TLB
11 * functions on the ARM610 & ARM710.
12 */
13#include <linux/linkage.h>
14#include <linux/init.h>
15#include <asm/assembler.h>
16#include <asm/constants.h>
17#include <asm/pgtable.h>
18#include <asm/procinfo.h>
19#include <asm/ptrace.h>
20
21ENTRY(cpu_arm6_dcache_clean_area)
22ENTRY(cpu_arm7_dcache_clean_area)
23 mov pc, lr
24
25/*
26 * Function: arm6_7_data_abort ()
27 *
28 * Params : r2 = address of aborted instruction
29 * : sp = pointer to registers
30 *
31 * Purpose : obtain information about current aborted instruction
32 *
33 * Returns : r0 = address of abort
34 * : r1 = FSR
35 */
36
37ENTRY(cpu_arm7_data_abort)
38 mrc p15, 0, r1, c5, c0, 0 @ get FSR
39 mrc p15, 0, r0, c6, c0, 0 @ get FAR
40 ldr r8, [r0] @ read arm instruction
41 tst r8, #1 << 20 @ L = 1 -> write?
42 orreq r1, r1, #1 << 8 @ yes.
43 and r7, r8, #15 << 24
44 add pc, pc, r7, lsr #22 @ Now branch to the relevant processing routine
45 nop
46
47/* 0 */ b .data_unknown
48/* 1 */ mov pc, lr @ swp
49/* 2 */ b .data_unknown
50/* 3 */ b .data_unknown
51/* 4 */ b .data_arm_lateldrpostconst @ ldr rd, [rn], #m
52/* 5 */ b .data_arm_lateldrpreconst @ ldr rd, [rn, #m]
53/* 6 */ b .data_arm_lateldrpostreg @ ldr rd, [rn], rm
54/* 7 */ b .data_arm_lateldrprereg @ ldr rd, [rn, rm]
55/* 8 */ b .data_arm_ldmstm @ ldm*a rn, <rlist>
56/* 9 */ b .data_arm_ldmstm @ ldm*b rn, <rlist>
57/* a */ b .data_unknown
58/* b */ b .data_unknown
59/* c */ mov pc, lr @ ldc rd, [rn], #m @ Same as ldr rd, [rn], #m
60/* d */ mov pc, lr @ ldc rd, [rn, #m]
61/* e */ b .data_unknown
62/* f */
63.data_unknown: @ Part of jumptable
64 mov r0, r2
65 mov r1, r8
66 mov r2, sp
67 bl baddataabort
68 b ret_from_exception
69
70ENTRY(cpu_arm6_data_abort)
71 mrc p15, 0, r1, c5, c0, 0 @ get FSR
72 mrc p15, 0, r0, c6, c0, 0 @ get FAR
73 ldr r8, [r2] @ read arm instruction
74 tst r8, #1 << 20 @ L = 1 -> write?
75 orreq r1, r1, #1 << 8 @ yes.
76 and r7, r8, #14 << 24
77 teq r7, #8 << 24 @ was it ldm/stm
78 movne pc, lr
79
80.data_arm_ldmstm:
81 tst r8, #1 << 21 @ check writeback bit
82 moveq pc, lr @ no writeback -> no fixup
83 mov r7, #0x11
84 orr r7, r7, #0x1100
85 and r6, r8, r7
86 and r2, r8, r7, lsl #1
87 add r6, r6, r2, lsr #1
88 and r2, r8, r7, lsl #2
89 add r6, r6, r2, lsr #2
90 and r2, r8, r7, lsl #3
91 add r6, r6, r2, lsr #3
92 add r6, r6, r6, lsr #8
93 add r6, r6, r6, lsr #4
94 and r6, r6, #15 @ r6 = no. of registers to transfer.
95 and r5, r8, #15 << 16 @ Extract 'n' from instruction
96 ldr r7, [sp, r5, lsr #14] @ Get register 'Rn'
97 tst r8, #1 << 23 @ Check U bit
98 subne r7, r7, r6, lsl #2 @ Undo increment
99 addeq r7, r7, r6, lsl #2 @ Undo decrement
100 str r7, [sp, r5, lsr #14] @ Put register 'Rn'
101 mov pc, lr
102
103.data_arm_apply_r6_and_rn:
104 and r5, r8, #15 << 16 @ Extract 'n' from instruction
105 ldr r7, [sp, r5, lsr #14] @ Get register 'Rn'
106 tst r8, #1 << 23 @ Check U bit
107 subne r7, r7, r6 @ Undo incrmenet
108 addeq r7, r7, r6 @ Undo decrement
109 str r7, [sp, r5, lsr #14] @ Put register 'Rn'
110 mov pc, lr
111
112.data_arm_lateldrpreconst:
113 tst r8, #1 << 21 @ check writeback bit
114 moveq pc, lr @ no writeback -> no fixup
115.data_arm_lateldrpostconst:
116 movs r2, r8, lsl #20 @ Get offset
117 moveq pc, lr @ zero -> no fixup
118 and r5, r8, #15 << 16 @ Extract 'n' from instruction
119 ldr r7, [sp, r5, lsr #14] @ Get register 'Rn'
120 tst r8, #1 << 23 @ Check U bit
121 subne r7, r7, r2, lsr #20 @ Undo increment
122 addeq r7, r7, r2, lsr #20 @ Undo decrement
123 str r7, [sp, r5, lsr #14] @ Put register 'Rn'
124 mov pc, lr
125
126.data_arm_lateldrprereg:
127 tst r8, #1 << 21 @ check writeback bit
128 moveq pc, lr @ no writeback -> no fixup
129.data_arm_lateldrpostreg:
130 and r7, r8, #15 @ Extract 'm' from instruction
131 ldr r6, [sp, r7, lsl #2] @ Get register 'Rm'
132 mov r5, r8, lsr #7 @ get shift count
133 ands r5, r5, #31
134 and r7, r8, #0x70 @ get shift type
135 orreq r7, r7, #8 @ shift count = 0
136 add pc, pc, r7
137 nop
138
139 mov r6, r6, lsl r5 @ 0: LSL #!0
140 b .data_arm_apply_r6_and_rn
141 b .data_arm_apply_r6_and_rn @ 1: LSL #0
142 nop
143 b .data_unknown @ 2: MUL?
144 nop
145 b .data_unknown @ 3: MUL?
146 nop
147 mov r6, r6, lsr r5 @ 4: LSR #!0
148 b .data_arm_apply_r6_and_rn
149 mov r6, r6, lsr #32 @ 5: LSR #32
150 b .data_arm_apply_r6_and_rn
151 b .data_unknown @ 6: MUL?
152 nop
153 b .data_unknown @ 7: MUL?
154 nop
155 mov r6, r6, asr r5 @ 8: ASR #!0
156 b .data_arm_apply_r6_and_rn
157 mov r6, r6, asr #32 @ 9: ASR #32
158 b .data_arm_apply_r6_and_rn
159 b .data_unknown @ A: MUL?
160 nop
161 b .data_unknown @ B: MUL?
162 nop
163 mov r6, r6, ror r5 @ C: ROR #!0
164 b .data_arm_apply_r6_and_rn
165 mov r6, r6, rrx @ D: RRX
166 b .data_arm_apply_r6_and_rn
167 b .data_unknown @ E: MUL?
168 nop
169 b .data_unknown @ F: MUL?
170
171/*
172 * Function: arm6_7_proc_init (void)
173 * : arm6_7_proc_fin (void)
174 *
175 * Notes : This processor does not require these
176 */
177ENTRY(cpu_arm6_proc_init)
178ENTRY(cpu_arm7_proc_init)
179 mov pc, lr
180
181ENTRY(cpu_arm6_proc_fin)
182ENTRY(cpu_arm7_proc_fin)
183 mov r0, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
184 msr cpsr_c, r0
185 mov r0, #0x31 @ ....S..DP...M
186 mcr p15, 0, r0, c1, c0, 0 @ disable caches
187 mov pc, lr
188
189ENTRY(cpu_arm6_do_idle)
190ENTRY(cpu_arm7_do_idle)
191 mov pc, lr
192
193/*
194 * Function: arm6_7_switch_mm(unsigned long pgd_phys)
195 * Params : pgd_phys Physical address of page table
196 * Purpose : Perform a task switch, saving the old processes state, and restoring
197 * the new.
198 */
199ENTRY(cpu_arm6_switch_mm)
200ENTRY(cpu_arm7_switch_mm)
201 mov r1, #0
202 mcr p15, 0, r1, c7, c0, 0 @ flush cache
203 mcr p15, 0, r0, c2, c0, 0 @ update page table ptr
204 mcr p15, 0, r1, c5, c0, 0 @ flush TLBs
205 mov pc, lr
206
207/*
208 * Function: arm6_7_set_pte(pte_t *ptep, pte_t pte)
209 * Params : r0 = Address to set
210 * : r1 = value to set
211 * Purpose : Set a PTE and flush it out of any WB cache
212 */
213 .align 5
214ENTRY(cpu_arm6_set_pte)
215ENTRY(cpu_arm7_set_pte)
216 str r1, [r0], #-2048 @ linux version
217
218 eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
219
220 bic r2, r1, #PTE_SMALL_AP_MASK
221 bic r2, r2, #PTE_TYPE_MASK
222 orr r2, r2, #PTE_TYPE_SMALL
223
224 tst r1, #L_PTE_USER @ User?
225 orrne r2, r2, #PTE_SMALL_AP_URO_SRW
226
227 tst r1, #L_PTE_WRITE | L_PTE_DIRTY @ Write and Dirty?
228 orreq r2, r2, #PTE_SMALL_AP_UNO_SRW
229
230 tst r1, #L_PTE_PRESENT | L_PTE_YOUNG @ Present and Young
231 movne r2, #0
232
233 str r2, [r0] @ hardware version
234 mov pc, lr
235
236/*
237 * Function: _arm6_7_reset
238 * Params : r0 = address to jump to
239 * Notes : This sets up everything for a reset
240 */
241ENTRY(cpu_arm6_reset)
242ENTRY(cpu_arm7_reset)
243 mov r1, #0
244 mcr p15, 0, r1, c7, c0, 0 @ flush cache
245 mcr p15, 0, r1, c5, c0, 0 @ flush TLB
246 mov r1, #0x30
247 mcr p15, 0, r1, c1, c0, 0 @ turn off MMU etc
248 mov pc, r0
249
250 __INIT
251
252 .type __arm6_setup, #function
253__arm6_setup: mov r0, #0
254 mcr p15, 0, r0, c7, c0 @ flush caches on v3
255 mcr p15, 0, r0, c5, c0 @ flush TLBs on v3
256 mov r0, #0x3d @ . ..RS BLDP WCAM
257 orr r0, r0, #0x100 @ . ..01 0011 1101
258 mov pc, lr
259 .size __arm6_setup, . - __arm6_setup
260
261 .type __arm7_setup, #function
262__arm7_setup: mov r0, #0
263 mcr p15, 0, r0, c7, c0 @ flush caches on v3
264 mcr p15, 0, r0, c5, c0 @ flush TLBs on v3
265 mcr p15, 0, r0, c3, c0 @ load domain access register
266 mov r0, #0x7d @ . ..RS BLDP WCAM
267 orr r0, r0, #0x100 @ . ..01 0111 1101
268 mov pc, lr
269 .size __arm7_setup, . - __arm7_setup
270
271 __INITDATA
272
273/*
274 * Purpose : Function pointers used to access above functions - all calls
275 * come through these
276 */
277 .type arm6_processor_functions, #object
278ENTRY(arm6_processor_functions)
279 .word cpu_arm6_data_abort
280 .word cpu_arm6_proc_init
281 .word cpu_arm6_proc_fin
282 .word cpu_arm6_reset
283 .word cpu_arm6_do_idle
284 .word cpu_arm6_dcache_clean_area
285 .word cpu_arm6_switch_mm
286 .word cpu_arm6_set_pte
287 .size arm6_processor_functions, . - arm6_processor_functions
288
289/*
290 * Purpose : Function pointers used to access above functions - all calls
291 * come through these
292 */
293 .type arm7_processor_functions, #object
294ENTRY(arm7_processor_functions)
295 .word cpu_arm7_data_abort
296 .word cpu_arm7_proc_init
297 .word cpu_arm7_proc_fin
298 .word cpu_arm7_reset
299 .word cpu_arm7_do_idle
300 .word cpu_arm7_dcache_clean_area
301 .word cpu_arm7_switch_mm
302 .word cpu_arm7_set_pte
303 .size arm7_processor_functions, . - arm7_processor_functions
304
305 .section ".rodata"
306
307 .type cpu_arch_name, #object
308cpu_arch_name: .asciz "armv3"
309 .size cpu_arch_name, . - cpu_arch_name
310
311 .type cpu_elf_name, #object
312cpu_elf_name: .asciz "v3"
313 .size cpu_elf_name, . - cpu_elf_name
314
315 .type cpu_arm6_name, #object
316cpu_arm6_name: .asciz "ARM6"
317 .size cpu_arm6_name, . - cpu_arm6_name
318
319 .type cpu_arm610_name, #object
320cpu_arm610_name:
321 .asciz "ARM610"
322 .size cpu_arm610_name, . - cpu_arm610_name
323
324 .type cpu_arm7_name, #object
325cpu_arm7_name: .asciz "ARM7"
326 .size cpu_arm7_name, . - cpu_arm7_name
327
328 .type cpu_arm710_name, #object
329cpu_arm710_name:
330 .asciz "ARM710"
331 .size cpu_arm710_name, . - cpu_arm710_name
332
333 .align
334
335 .section ".proc.info", #alloc, #execinstr
336
337 .type __arm6_proc_info, #object
338__arm6_proc_info:
339 .long 0x41560600
340 .long 0xfffffff0
341 .long 0x00000c1e
342 b __arm6_setup
343 .long cpu_arch_name
344 .long cpu_elf_name
345 .long HWCAP_SWP | HWCAP_26BIT
346 .long cpu_arm6_name
347 .long arm6_processor_functions
348 .long v3_tlb_fns
349 .long v3_user_fns
350 .long v3_cache_fns
351 .size __arm6_proc_info, . - __arm6_proc_info
352
353 .type __arm610_proc_info, #object
354__arm610_proc_info:
355 .long 0x41560610
356 .long 0xfffffff0
357 .long 0x00000c1e
358 b __arm6_setup
359 .long cpu_arch_name
360 .long cpu_elf_name
361 .long HWCAP_SWP | HWCAP_26BIT
362 .long cpu_arm610_name
363 .long arm6_processor_functions
364 .long v3_tlb_fns
365 .long v3_user_fns
366 .long v3_cache_fns
367 .size __arm610_proc_info, . - __arm610_proc_info
368
369 .type __arm7_proc_info, #object
370__arm7_proc_info:
371 .long 0x41007000
372 .long 0xffffff00
373 .long 0x00000c1e
374 b __arm7_setup
375 .long cpu_arch_name
376 .long cpu_elf_name
377 .long HWCAP_SWP | HWCAP_26BIT
378 .long cpu_arm7_name
379 .long arm7_processor_functions
380 .long v3_tlb_fns
381 .long v3_user_fns
382 .long v3_cache_fns
383 .size __arm7_proc_info, . - __arm7_proc_info
384
385 .type __arm710_proc_info, #object
386__arm710_proc_info:
387 .long 0x41007100
388 .long 0xfff8ff00
389 .long PMD_TYPE_SECT | \
390 PMD_SECT_BUFFERABLE | \
391 PMD_SECT_CACHEABLE | \
392 PMD_BIT4 | \
393 PMD_SECT_AP_WRITE | \
394 PMD_SECT_AP_READ
395 b __arm7_setup
396 .long cpu_arch_name
397 .long cpu_elf_name
398 .long HWCAP_SWP | HWCAP_26BIT
399 .long cpu_arm710_name
400 .long arm7_processor_functions
401 .long v3_tlb_fns
402 .long v3_user_fns
403 .long v3_cache_fns
404 .size __arm710_proc_info, . - __arm710_proc_info
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-12 07:20:27 -0500