diff options
author | Russell King <rmk+kernel@arm.linux.org.uk> | 2010-07-26 07:22:12 -0400 |
---|---|---|
committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2010-07-27 05:48:42 -0400 |
commit | 9ca03a21e320a6bf44559323527aba704bcc8772 (patch) | |
tree | c3422c49decfdca220c0088938546c49ee71ba64 /arch/arm/mm/proc-arm1026.S | |
parent | b8ab5397bcbd92e3fd4a9770e0bf59315fa38dab (diff) |
ARM: Factor out common code from cpu_proc_fin()
All implementations of cpu_proc_fin() start by disabling interrupts
and then flush caches. Rather than have every processors proc_fin()
implementation do this, move it out into generic code - and move the
cache flush past setup_mm_for_reboot() (so it can benefit from having
caches still enabled.)
This allows cpu_proc_fin() to become independent of the L1/L2 cache
types, and eventually move the L2 cache flushing into the L2 support
code.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mm/proc-arm1026.S')
-rw-r--r-- | arch/arm/mm/proc-arm1026.S | 6 |
1 files changed, 1 insertions, 5 deletions
diff --git a/arch/arm/mm/proc-arm1026.S b/arch/arm/mm/proc-arm1026.S index 636672a29c6d..5697c34b95b0 100644 --- a/arch/arm/mm/proc-arm1026.S +++ b/arch/arm/mm/proc-arm1026.S | |||
@@ -68,15 +68,11 @@ ENTRY(cpu_arm1026_proc_init) | |||
68 | * cpu_arm1026_proc_fin() | 68 | * cpu_arm1026_proc_fin() |
69 | */ | 69 | */ |
70 | ENTRY(cpu_arm1026_proc_fin) | 70 | ENTRY(cpu_arm1026_proc_fin) |
71 | stmfd sp!, {lr} | ||
72 | mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE | ||
73 | msr cpsr_c, ip | ||
74 | bl arm1026_flush_kern_cache_all | ||
75 | mrc p15, 0, r0, c1, c0, 0 @ ctrl register | 71 | mrc p15, 0, r0, c1, c0, 0 @ ctrl register |
76 | bic r0, r0, #0x1000 @ ...i............ | 72 | bic r0, r0, #0x1000 @ ...i............ |
77 | bic r0, r0, #0x000e @ ............wca. | 73 | bic r0, r0, #0x000e @ ............wca. |
78 | mcr p15, 0, r0, c1, c0, 0 @ disable caches | 74 | mcr p15, 0, r0, c1, c0, 0 @ disable caches |
79 | ldmfd sp!, {pc} | 75 | mov pc, lr |
80 | 76 | ||
81 | /* | 77 | /* |
82 | * cpu_arm1026_reset(loc) | 78 | * cpu_arm1026_reset(loc) |