diff options
author | Hyok S. Choi <hyok.choi@samsung.com> | 2006-06-28 09:10:01 -0400 |
---|---|---|
committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2006-06-28 12:59:56 -0400 |
commit | d090dddaba7c8da6401bb259340dce05ca32f564 (patch) | |
tree | c35d9e22dc09d40144b4a672962269ff60c9ad07 /arch/arm/mm/proc-arm1022.S | |
parent | a4f7e76367f7775ecf534a37b4623c83d9d7ba74 (diff) |
[ARM] nommu: Initial uCLinux support for MMU-based CPUs
In noMMU mode, various of functions which are defined in mm/proc-*.S
is not valid or needed to be avoided. i.g. switch_mm is not needed,
just returns and this makes the I & D caches are valid which shows
great improvement of performance including task switching and IPC.
Signed-off-by: Hyok S. Choi <hyok.choi@samsung.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mm/proc-arm1022.S')
-rw-r--r-- | arch/arm/mm/proc-arm1022.S | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/arch/arm/mm/proc-arm1022.S b/arch/arm/mm/proc-arm1022.S index f778545d57a2..b0ccff4fadd2 100644 --- a/arch/arm/mm/proc-arm1022.S +++ b/arch/arm/mm/proc-arm1022.S | |||
@@ -3,6 +3,7 @@ | |||
3 | * | 3 | * |
4 | * Copyright (C) 2000 ARM Limited | 4 | * Copyright (C) 2000 ARM Limited |
5 | * Copyright (C) 2000 Deep Blue Solutions Ltd. | 5 | * Copyright (C) 2000 Deep Blue Solutions Ltd. |
6 | * hacked for non-paged-MM by Hyok S. Choi, 2003. | ||
6 | * | 7 | * |
7 | * This program is free software; you can redistribute it and/or modify | 8 | * This program is free software; you can redistribute it and/or modify |
8 | * it under the terms of the GNU General Public License as published by | 9 | * it under the terms of the GNU General Public License as published by |
@@ -90,7 +91,9 @@ ENTRY(cpu_arm1022_reset) | |||
90 | mov ip, #0 | 91 | mov ip, #0 |
91 | mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches | 92 | mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches |
92 | mcr p15, 0, ip, c7, c10, 4 @ drain WB | 93 | mcr p15, 0, ip, c7, c10, 4 @ drain WB |
94 | #ifdef CONFIG_MMU | ||
93 | mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs | 95 | mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs |
96 | #endif | ||
94 | mrc p15, 0, ip, c1, c0, 0 @ ctrl register | 97 | mrc p15, 0, ip, c1, c0, 0 @ ctrl register |
95 | bic ip, ip, #0x000f @ ............wcam | 98 | bic ip, ip, #0x000f @ ............wcam |
96 | bic ip, ip, #0x1100 @ ...i...s........ | 99 | bic ip, ip, #0x1100 @ ...i...s........ |
@@ -333,6 +336,7 @@ ENTRY(cpu_arm1022_dcache_clean_area) | |||
333 | */ | 336 | */ |
334 | .align 5 | 337 | .align 5 |
335 | ENTRY(cpu_arm1022_switch_mm) | 338 | ENTRY(cpu_arm1022_switch_mm) |
339 | #ifdef CONFIG_MMU | ||
336 | #ifndef CONFIG_CPU_DCACHE_DISABLE | 340 | #ifndef CONFIG_CPU_DCACHE_DISABLE |
337 | mov r1, #(CACHE_DSEGMENTS - 1) << 5 @ 16 segments | 341 | mov r1, #(CACHE_DSEGMENTS - 1) << 5 @ 16 segments |
338 | 1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries | 342 | 1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries |
@@ -349,6 +353,7 @@ ENTRY(cpu_arm1022_switch_mm) | |||
349 | mcr p15, 0, r1, c7, c10, 4 @ drain WB | 353 | mcr p15, 0, r1, c7, c10, 4 @ drain WB |
350 | mcr p15, 0, r0, c2, c0, 0 @ load page table pointer | 354 | mcr p15, 0, r0, c2, c0, 0 @ load page table pointer |
351 | mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs | 355 | mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs |
356 | #endif | ||
352 | mov pc, lr | 357 | mov pc, lr |
353 | 358 | ||
354 | /* | 359 | /* |
@@ -358,6 +363,7 @@ ENTRY(cpu_arm1022_switch_mm) | |||
358 | */ | 363 | */ |
359 | .align 5 | 364 | .align 5 |
360 | ENTRY(cpu_arm1022_set_pte) | 365 | ENTRY(cpu_arm1022_set_pte) |
366 | #ifdef CONFIG_MMU | ||
361 | str r1, [r0], #-2048 @ linux version | 367 | str r1, [r0], #-2048 @ linux version |
362 | 368 | ||
363 | eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY | 369 | eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY |
@@ -385,6 +391,7 @@ ENTRY(cpu_arm1022_set_pte) | |||
385 | #ifndef CONFIG_CPU_DCACHE_DISABLE | 391 | #ifndef CONFIG_CPU_DCACHE_DISABLE |
386 | mcr p15, 0, r0, c7, c10, 1 @ clean D entry | 392 | mcr p15, 0, r0, c7, c10, 1 @ clean D entry |
387 | #endif | 393 | #endif |
394 | #endif /* CONFIG_MMU */ | ||
388 | mov pc, lr | 395 | mov pc, lr |
389 | 396 | ||
390 | __INIT | 397 | __INIT |
@@ -394,7 +401,9 @@ __arm1022_setup: | |||
394 | mov r0, #0 | 401 | mov r0, #0 |
395 | mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4 | 402 | mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4 |
396 | mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4 | 403 | mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4 |
404 | #ifdef CONFIG_MMU | ||
397 | mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4 | 405 | mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4 |
406 | #endif | ||
398 | mrc p15, 0, r0, c1, c0 @ get control register v4 | 407 | mrc p15, 0, r0, c1, c0 @ get control register v4 |
399 | ldr r5, arm1022_cr1_clear | 408 | ldr r5, arm1022_cr1_clear |
400 | bic r0, r0, r5 | 409 | bic r0, r0, r5 |