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authorLinus Torvalds <torvalds@g5.osdl.org>2006-07-02 18:04:12 -0400
committerLinus Torvalds <torvalds@g5.osdl.org>2006-07-02 18:04:12 -0400
commita8c4c20dfa8b28a3c99e33c639d9c2ea5657741e (patch)
tree887b64d29b5a46d9ab2ca1267d8a2f05b5845561 /arch/arm/mm/proc-arm1022.S
parent168d04b3b4de7723eb73b3cffc9cb75224e0f393 (diff)
parent2dc7667b9d0674db6572723356fe3857031101a4 (diff)
Merge branch 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm
* 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm: (44 commits) [ARM] 3541/2: workaround for PXA27x erratum E7 [ARM] nommu: provide a way for correct control register value selection [ARM] 3705/1: add supersection support to ioremap() [ARM] 3707/1: iwmmxt: use the generic thread notifier infrastructure [ARM] 3706/2: ep93xx: add cirrus logic edb9315a support [ARM] 3704/1: format IOP Kconfig with tabs, create more consistency [ARM] 3703/1: Add help description for ARCH_EP80219 [ARM] 3678/1: MMC: Make OMAP MMC work [ARM] 3677/1: OMAP: Update H2 defconfig [ARM] 3676/1: ARM: OMAP: Fix dmtimers and timer32k to compile on OMAP1 [ARM] Add section support to ioremap [ARM] Fix sa11x0 SDRAM selection [ARM] Set bit 4 on section mappings correctly depending on CPU [ARM] 3666/1: TRIZEPS4 [1/5] core ARM: OMAP: Multiplexing for 24xx GPMC wait pin monitoring ARM: OMAP: Fix SRAM to use MT_MEMORY instead of MT_DEVICE ARM: OMAP: Update dmtimers ARM: OMAP: Make clock variables static ARM: OMAP: Fix GPMC compilation when DEBUG is defined ARM: OMAP: Mux updates for external DMA and GPIO ...
Diffstat (limited to 'arch/arm/mm/proc-arm1022.S')
-rw-r--r--arch/arm/mm/proc-arm1022.S39
1 files changed, 11 insertions, 28 deletions
diff --git a/arch/arm/mm/proc-arm1022.S b/arch/arm/mm/proc-arm1022.S
index 39b7c102180a..566a55653072 100644
--- a/arch/arm/mm/proc-arm1022.S
+++ b/arch/arm/mm/proc-arm1022.S
@@ -403,11 +403,11 @@ __arm1022_setup:
403#ifdef CONFIG_MMU 403#ifdef CONFIG_MMU
404 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4 404 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
405#endif 405#endif
406 adr r5, arm1022_crval
407 ldmia r5, {r5, r6}
406 mrc p15, 0, r0, c1, c0 @ get control register v4 408 mrc p15, 0, r0, c1, c0 @ get control register v4
407 ldr r5, arm1022_cr1_clear
408 bic r0, r0, r5 409 bic r0, r0, r5
409 ldr r5, arm1022_cr1_set 410 orr r0, r0, r6
410 orr r0, r0, r5
411#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN 411#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
412 orr r0, r0, #0x4000 @ .R.............. 412 orr r0, r0, #0x4000 @ .R..............
413#endif 413#endif
@@ -420,12 +420,9 @@ __arm1022_setup:
420 * .011 1001 ..11 0101 420 * .011 1001 ..11 0101
421 * 421 *
422 */ 422 */
423 .type arm1022_cr1_clear, #object 423 .type arm1022_crval, #object
424 .type arm1022_cr1_set, #object 424arm1022_crval:
425arm1022_cr1_clear: 425 crval clear=0x00007f3f, mmuset=0x00003935, ucset=0x00001930
426 .word 0x7f3f
427arm1022_cr1_set:
428 .word 0x3935
429 426
430 __INITDATA 427 __INITDATA
431 428
@@ -459,25 +456,7 @@ cpu_elf_name:
459 456
460 .type cpu_arm1022_name, #object 457 .type cpu_arm1022_name, #object
461cpu_arm1022_name: 458cpu_arm1022_name:
462 .ascii "arm1022" 459 .asciz "ARM1022"
463#ifndef CONFIG_CPU_ICACHE_DISABLE
464 .ascii "i"
465#endif
466#ifndef CONFIG_CPU_DCACHE_DISABLE
467 .ascii "d"
468#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
469 .ascii "(wt)"
470#else
471 .ascii "(wb)"
472#endif
473#endif
474#ifndef CONFIG_CPU_BPREDICT_DISABLE
475 .ascii "B"
476#endif
477#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
478 .ascii "RR"
479#endif
480 .ascii "\0"
481 .size cpu_arm1022_name, . - cpu_arm1022_name 460 .size cpu_arm1022_name, . - cpu_arm1022_name
482 461
483 .align 462 .align
@@ -492,6 +471,10 @@ __arm1022_proc_info:
492 PMD_BIT4 | \ 471 PMD_BIT4 | \
493 PMD_SECT_AP_WRITE | \ 472 PMD_SECT_AP_WRITE | \
494 PMD_SECT_AP_READ 473 PMD_SECT_AP_READ
474 .long PMD_TYPE_SECT | \
475 PMD_BIT4 | \
476 PMD_SECT_AP_WRITE | \
477 PMD_SECT_AP_READ
495 b __arm1022_setup 478 b __arm1022_setup
496 .long cpu_arch_name 479 .long cpu_arch_name
497 .long cpu_elf_name 480 .long cpu_elf_name