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authorRussell King <rmk@dyn-67.arm.linux.org.uk>2006-06-29 13:24:21 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2006-06-29 13:24:21 -0400
commit8799ee9f49f6171fd58f4d64f8c067ca49006a5d (patch)
treeb746b8800bc99633f31505d151624c8ccd75cd47 /arch/arm/mm/proc-arm1020.S
parent326764a85b7676388db3ebad6488f312631d7661 (diff)
[ARM] Set bit 4 on section mappings correctly depending on CPU
On some CPUs, bit 4 of section mappings means "update the cache when written to". On others, this bit is required to be one, and others it's required to be zero. Finally, on ARMv6 and above, setting it turns on "no execute" and prevents speculative prefetches. With all these combinations, no one value fits all CPUs, so we have to pick a value depending on the CPU type, and the area we're mapping. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mm/proc-arm1020.S')
-rw-r--r--arch/arm/mm/proc-arm1020.S3
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/arm/mm/proc-arm1020.S b/arch/arm/mm/proc-arm1020.S
index b9abbafca812..efeebe77891f 100644
--- a/arch/arm/mm/proc-arm1020.S
+++ b/arch/arm/mm/proc-arm1020.S
@@ -527,6 +527,9 @@ __arm1020_proc_info:
527 .long PMD_TYPE_SECT | \ 527 .long PMD_TYPE_SECT | \
528 PMD_SECT_AP_WRITE | \ 528 PMD_SECT_AP_WRITE | \
529 PMD_SECT_AP_READ 529 PMD_SECT_AP_READ
530 .long PMD_TYPE_SECT | \
531 PMD_SECT_AP_WRITE | \
532 PMD_SECT_AP_READ
530 b __arm1020_setup 533 b __arm1020_setup
531 .long cpu_arch_name 534 .long cpu_arch_name
532 .long cpu_elf_name 535 .long cpu_elf_name