aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm/mm/proc-arm1020.S
diff options
context:
space:
mode:
authorCatalin Marinas <catalin.marinas@arm.com>2005-06-30 12:04:14 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2005-06-30 12:04:14 -0400
commitabaf48a05a8f097654e746af2a5afb2ab95861a1 (patch)
tree80cd0d34086e3cb8c1781e317b49c84ad6c97841 /arch/arm/mm/proc-arm1020.S
parentc28a814f25d48f193565003223df0ae617796892 (diff)
[PATCH] ARM: 2779/1: Fix the V bit setting for the ARM1020x CPUs
Patch from Catalin Marinas This patch fixes the V bit setting for the ARM1020x processors. At reset, this bit is automatically set to the value of the HIVECSINIT input signal which just happened to be 1 but it is not mandatory. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mm/proc-arm1020.S')
-rw-r--r--arch/arm/mm/proc-arm1020.S4
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/mm/proc-arm1020.S b/arch/arm/mm/proc-arm1020.S
index e69f1940ab39..5c0ae5260d1c 100644
--- a/arch/arm/mm/proc-arm1020.S
+++ b/arch/arm/mm/proc-arm1020.S
@@ -445,14 +445,14 @@ __arm1020_setup:
445 /* 445 /*
446 * R 446 * R
447 * .RVI ZFRS BLDP WCAM 447 * .RVI ZFRS BLDP WCAM
448 * .0.1 1001 ..11 0101 FIXME: why no V bit? 448 * .011 1001 ..11 0101
449 */ 449 */
450 .type arm1020_cr1_clear, #object 450 .type arm1020_cr1_clear, #object
451 .type arm1020_cr1_set, #object 451 .type arm1020_cr1_set, #object
452arm1020_cr1_clear: 452arm1020_cr1_clear:
453 .word 0x593f 453 .word 0x593f
454arm1020_cr1_set: 454arm1020_cr1_set:
455 .word 0x1935 455 .word 0x3935
456 456
457 __INITDATA 457 __INITDATA
458 458