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authorKirill A. Shutemov <kirill@shutemov.name>2009-09-25 08:39:47 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2009-10-02 17:34:32 -0400
commit4fb2847437d871fe579f820ceb18031db3359901 (patch)
treee2015dbc54178dd114eb0c41fa5a29d89dd15b41 /arch/arm/mm/proc-arm1020.S
parent6806bfe18fca92e2001538b84cab5f63c5ea4bed (diff)
ARM: 5727/1: Pass IFSR register to do_PrefetchAbort()
Instruction fault status register, IFSR, was introduced on ARMv6 to provide status information about the last insturction fault. It needed for proper prefetch abort handling. Now we have three prefetch abort model: * legacy - for CPUs before ARMv6. They doesn't provide neither IFSR nor IFAR. We simulate IFSR with section translation fault status for them to generalize code; * ARMv6 - provides IFSR, but not IFAR; * ARMv7 - provides both IFSR and IFAR. Signed-off-by: Kirill A. Shutemov <kirill@shutemov.name> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mm/proc-arm1020.S')
-rw-r--r--arch/arm/mm/proc-arm1020.S2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mm/proc-arm1020.S b/arch/arm/mm/proc-arm1020.S
index b5551bf010aa..d9fb4b98c49f 100644
--- a/arch/arm/mm/proc-arm1020.S
+++ b/arch/arm/mm/proc-arm1020.S
@@ -449,7 +449,7 @@ arm1020_crval:
449 .type arm1020_processor_functions, #object 449 .type arm1020_processor_functions, #object
450arm1020_processor_functions: 450arm1020_processor_functions:
451 .word v4t_early_abort 451 .word v4t_early_abort
452 .word pabort_noifar 452 .word legacy_pabort
453 .word cpu_arm1020_proc_init 453 .word cpu_arm1020_proc_init
454 .word cpu_arm1020_proc_fin 454 .word cpu_arm1020_proc_fin
455 .word cpu_arm1020_reset 455 .word cpu_arm1020_reset