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authorRussell King <rmk+kernel@arm.linux.org.uk>2009-12-04 09:59:47 -0500
committerRussell King <rmk+kernel@arm.linux.org.uk>2009-12-04 09:59:47 -0500
commit5cb2faa6ede7ada9cb2bffc832c4ce60f53d6834 (patch)
tree7b72b66081d042a41dc822575503133364857ce2 /arch/arm/mm/mmu.c
parente0ee98513d1a2e24d2ddbdecf4216bcca29d1158 (diff)
parent6060e8df517847bf445ebc61de7d4d9c7faae990 (diff)
Merge branch 'pending-misc' (early part) into devel
Diffstat (limited to 'arch/arm/mm/mmu.c')
-rw-r--r--arch/arm/mm/mmu.c9
1 files changed, 8 insertions, 1 deletions
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index 02243eeccf50..2427cdcd9098 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -117,6 +117,13 @@ static void __init early_cachepolicy(char **p)
117 } 117 }
118 if (i == ARRAY_SIZE(cache_policies)) 118 if (i == ARRAY_SIZE(cache_policies))
119 printk(KERN_ERR "ERROR: unknown or unsupported cache policy\n"); 119 printk(KERN_ERR "ERROR: unknown or unsupported cache policy\n");
120 /*
121 * This restriction is partly to do with the way we boot; it is
122 * unpredictable to have memory mapped using two different sets of
123 * memory attributes (shared, type, and cache attribs). We can not
124 * change these attributes once the initial assembly has setup the
125 * page tables.
126 */
120 if (cpu_architecture() >= CPU_ARCH_ARMv6) { 127 if (cpu_architecture() >= CPU_ARCH_ARMv6) {
121 printk(KERN_WARNING "Only cachepolicy=writeback supported on ARMv6 and later\n"); 128 printk(KERN_WARNING "Only cachepolicy=writeback supported on ARMv6 and later\n");
122 cachepolicy = CPOLICY_WRITEBACK; 129 cachepolicy = CPOLICY_WRITEBACK;
@@ -1029,7 +1036,7 @@ void __init paging_init(struct machine_desc *mdesc)
1029 */ 1036 */
1030 zero_page = alloc_bootmem_low_pages(PAGE_SIZE); 1037 zero_page = alloc_bootmem_low_pages(PAGE_SIZE);
1031 empty_zero_page = virt_to_page(zero_page); 1038 empty_zero_page = virt_to_page(zero_page);
1032 flush_dcache_page(empty_zero_page); 1039 __flush_dcache_page(NULL, empty_zero_page);
1033} 1040}
1034 1041
1035/* 1042/*