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authorRussell King <rmk@dyn-67.arm.linux.org.uk>2006-09-27 10:38:34 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2006-09-27 10:38:34 -0400
commitae8f154129e4d965771c2d6adbe36210b3913d72 (patch)
treea0ae19dfe29e7a2f3b9db1f081b643eafc71d221 /arch/arm/mm/mm-armv.c
parentd111e8f9644aa585c1a7e198d74a4d2682ef1374 (diff)
[ARM] Move rest of MMU setup code from mm-armv.c to mmu.c
If we're going to have mmu.c for code which is specific to the MMU machines, we might as well move the other MMU initialisation specific code from mm-armv.c into this new file. This also allows us to make some functions static. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mm/mm-armv.c')
-rw-r--r--arch/arm/mm/mm-armv.c550
1 files changed, 0 insertions, 550 deletions
diff --git a/arch/arm/mm/mm-armv.c b/arch/arm/mm/mm-armv.c
index ee9647823fad..a35d5f2ee4e0 100644
--- a/arch/arm/mm/mm-armv.c
+++ b/arch/arm/mm/mm-armv.c
@@ -9,137 +9,15 @@
9 * 9 *
10 * Page table sludge for ARM v3 and v4 processor architectures. 10 * Page table sludge for ARM v3 and v4 processor architectures.
11 */ 11 */
12#include <linux/module.h>
13#include <linux/mm.h> 12#include <linux/mm.h>
14#include <linux/init.h>
15#include <linux/bootmem.h>
16#include <linux/highmem.h> 13#include <linux/highmem.h>
17#include <linux/nodemask.h>
18 14
19#include <asm/pgalloc.h> 15#include <asm/pgalloc.h>
20#include <asm/page.h> 16#include <asm/page.h>
21#include <asm/setup.h>
22#include <asm/tlbflush.h> 17#include <asm/tlbflush.h>
23 18
24#include <asm/mach/map.h>
25
26#include "mm.h" 19#include "mm.h"
27 20
28#define CPOLICY_UNCACHED 0
29#define CPOLICY_BUFFERED 1
30#define CPOLICY_WRITETHROUGH 2
31#define CPOLICY_WRITEBACK 3
32#define CPOLICY_WRITEALLOC 4
33
34static unsigned int cachepolicy __initdata = CPOLICY_WRITEBACK;
35static unsigned int ecc_mask __initdata = 0;
36pgprot_t pgprot_kernel;
37
38EXPORT_SYMBOL(pgprot_kernel);
39
40struct cachepolicy {
41 const char policy[16];
42 unsigned int cr_mask;
43 unsigned int pmd;
44 unsigned int pte;
45};
46
47static struct cachepolicy cache_policies[] __initdata = {
48 {
49 .policy = "uncached",
50 .cr_mask = CR_W|CR_C,
51 .pmd = PMD_SECT_UNCACHED,
52 .pte = 0,
53 }, {
54 .policy = "buffered",
55 .cr_mask = CR_C,
56 .pmd = PMD_SECT_BUFFERED,
57 .pte = PTE_BUFFERABLE,
58 }, {
59 .policy = "writethrough",
60 .cr_mask = 0,
61 .pmd = PMD_SECT_WT,
62 .pte = PTE_CACHEABLE,
63 }, {
64 .policy = "writeback",
65 .cr_mask = 0,
66 .pmd = PMD_SECT_WB,
67 .pte = PTE_BUFFERABLE|PTE_CACHEABLE,
68 }, {
69 .policy = "writealloc",
70 .cr_mask = 0,
71 .pmd = PMD_SECT_WBWA,
72 .pte = PTE_BUFFERABLE|PTE_CACHEABLE,
73 }
74};
75
76/*
77 * These are useful for identifing cache coherency
78 * problems by allowing the cache or the cache and
79 * writebuffer to be turned off. (Note: the write
80 * buffer should not be on and the cache off).
81 */
82static void __init early_cachepolicy(char **p)
83{
84 int i;
85
86 for (i = 0; i < ARRAY_SIZE(cache_policies); i++) {
87 int len = strlen(cache_policies[i].policy);
88
89 if (memcmp(*p, cache_policies[i].policy, len) == 0) {
90 cachepolicy = i;
91 cr_alignment &= ~cache_policies[i].cr_mask;
92 cr_no_alignment &= ~cache_policies[i].cr_mask;
93 *p += len;
94 break;
95 }
96 }
97 if (i == ARRAY_SIZE(cache_policies))
98 printk(KERN_ERR "ERROR: unknown or unsupported cache policy\n");
99 flush_cache_all();
100 set_cr(cr_alignment);
101}
102
103static void __init early_nocache(char **__unused)
104{
105 char *p = "buffered";
106 printk(KERN_WARNING "nocache is deprecated; use cachepolicy=%s\n", p);
107 early_cachepolicy(&p);
108}
109
110static void __init early_nowrite(char **__unused)
111{
112 char *p = "uncached";
113 printk(KERN_WARNING "nowb is deprecated; use cachepolicy=%s\n", p);
114 early_cachepolicy(&p);
115}
116
117static void __init early_ecc(char **p)
118{
119 if (memcmp(*p, "on", 2) == 0) {
120 ecc_mask = PMD_PROTECTION;
121 *p += 2;
122 } else if (memcmp(*p, "off", 3) == 0) {
123 ecc_mask = 0;
124 *p += 3;
125 }
126}
127
128__early_param("nocache", early_nocache);
129__early_param("nowb", early_nowrite);
130__early_param("cachepolicy=", early_cachepolicy);
131__early_param("ecc=", early_ecc);
132
133static int __init noalign_setup(char *__unused)
134{
135 cr_alignment &= ~CR_A;
136 cr_no_alignment &= ~CR_A;
137 set_cr(cr_alignment);
138 return 1;
139}
140
141__setup("noalign", noalign_setup);
142
143#define FIRST_KERNEL_PGD_NR (FIRST_USER_PGD_NR + USER_PTRS_PER_PGD) 21#define FIRST_KERNEL_PGD_NR (FIRST_USER_PGD_NR + USER_PTRS_PER_PGD)
144 22
145/* 23/*
@@ -223,431 +101,3 @@ void free_pgd_slow(pgd_t *pgd)
223free: 101free:
224 free_pages((unsigned long) pgd, 2); 102 free_pages((unsigned long) pgd, 2);
225} 103}
226
227/*
228 * Create a SECTION PGD between VIRT and PHYS in domain
229 * DOMAIN with protection PROT. This operates on half-
230 * pgdir entry increments.
231 */
232static inline void
233alloc_init_section(unsigned long virt, unsigned long phys, int prot)
234{
235 pmd_t *pmdp = pmd_off_k(virt);
236
237 if (virt & (1 << 20))
238 pmdp++;
239
240 *pmdp = __pmd(phys | prot);
241 flush_pmd_entry(pmdp);
242}
243
244/*
245 * Create a SUPER SECTION PGD between VIRT and PHYS with protection PROT
246 */
247static inline void
248alloc_init_supersection(unsigned long virt, unsigned long phys, int prot)
249{
250 int i;
251
252 for (i = 0; i < 16; i += 1) {
253 alloc_init_section(virt, phys, prot | PMD_SECT_SUPER);
254
255 virt += (PGDIR_SIZE / 2);
256 }
257}
258
259/*
260 * Add a PAGE mapping between VIRT and PHYS in domain
261 * DOMAIN with protection PROT. Note that due to the
262 * way we map the PTEs, we must allocate two PTE_SIZE'd
263 * blocks - one for the Linux pte table, and one for
264 * the hardware pte table.
265 */
266static inline void
267alloc_init_page(unsigned long virt, unsigned long phys, unsigned int prot_l1, pgprot_t prot)
268{
269 pmd_t *pmdp = pmd_off_k(virt);
270 pte_t *ptep;
271
272 if (pmd_none(*pmdp)) {
273 ptep = alloc_bootmem_low_pages(2 * PTRS_PER_PTE *
274 sizeof(pte_t));
275
276 __pmd_populate(pmdp, __pa(ptep) | prot_l1);
277 }
278 ptep = pte_offset_kernel(pmdp, virt);
279
280 set_pte(ptep, pfn_pte(phys >> PAGE_SHIFT, prot));
281}
282
283struct mem_types {
284 unsigned int prot_pte;
285 unsigned int prot_l1;
286 unsigned int prot_sect;
287 unsigned int domain;
288};
289
290static struct mem_types mem_types[] __initdata = {
291 [MT_DEVICE] = {
292 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
293 L_PTE_WRITE,
294 .prot_l1 = PMD_TYPE_TABLE,
295 .prot_sect = PMD_TYPE_SECT | PMD_BIT4 | PMD_SECT_UNCACHED |
296 PMD_SECT_AP_WRITE,
297 .domain = DOMAIN_IO,
298 },
299 [MT_CACHECLEAN] = {
300 .prot_sect = PMD_TYPE_SECT | PMD_BIT4,
301 .domain = DOMAIN_KERNEL,
302 },
303 [MT_MINICLEAN] = {
304 .prot_sect = PMD_TYPE_SECT | PMD_BIT4 | PMD_SECT_MINICACHE,
305 .domain = DOMAIN_KERNEL,
306 },
307 [MT_LOW_VECTORS] = {
308 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
309 L_PTE_EXEC,
310 .prot_l1 = PMD_TYPE_TABLE,
311 .domain = DOMAIN_USER,
312 },
313 [MT_HIGH_VECTORS] = {
314 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
315 L_PTE_USER | L_PTE_EXEC,
316 .prot_l1 = PMD_TYPE_TABLE,
317 .domain = DOMAIN_USER,
318 },
319 [MT_MEMORY] = {
320 .prot_sect = PMD_TYPE_SECT | PMD_BIT4 | PMD_SECT_AP_WRITE,
321 .domain = DOMAIN_KERNEL,
322 },
323 [MT_ROM] = {
324 .prot_sect = PMD_TYPE_SECT | PMD_BIT4,
325 .domain = DOMAIN_KERNEL,
326 },
327 [MT_IXP2000_DEVICE] = { /* IXP2400 requires XCB=101 for on-chip I/O */
328 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
329 L_PTE_WRITE,
330 .prot_l1 = PMD_TYPE_TABLE,
331 .prot_sect = PMD_TYPE_SECT | PMD_BIT4 | PMD_SECT_UNCACHED |
332 PMD_SECT_AP_WRITE | PMD_SECT_BUFFERABLE |
333 PMD_SECT_TEX(1),
334 .domain = DOMAIN_IO,
335 },
336 [MT_NONSHARED_DEVICE] = {
337 .prot_l1 = PMD_TYPE_TABLE,
338 .prot_sect = PMD_TYPE_SECT | PMD_BIT4 | PMD_SECT_NONSHARED_DEV |
339 PMD_SECT_AP_WRITE,
340 .domain = DOMAIN_IO,
341 }
342};
343
344/*
345 * Adjust the PMD section entries according to the CPU in use.
346 */
347void __init build_mem_type_table(void)
348{
349 struct cachepolicy *cp;
350 unsigned int cr = get_cr();
351 unsigned int user_pgprot, kern_pgprot;
352 int cpu_arch = cpu_architecture();
353 int i;
354
355#if defined(CONFIG_CPU_DCACHE_DISABLE)
356 if (cachepolicy > CPOLICY_BUFFERED)
357 cachepolicy = CPOLICY_BUFFERED;
358#elif defined(CONFIG_CPU_DCACHE_WRITETHROUGH)
359 if (cachepolicy > CPOLICY_WRITETHROUGH)
360 cachepolicy = CPOLICY_WRITETHROUGH;
361#endif
362 if (cpu_arch < CPU_ARCH_ARMv5) {
363 if (cachepolicy >= CPOLICY_WRITEALLOC)
364 cachepolicy = CPOLICY_WRITEBACK;
365 ecc_mask = 0;
366 }
367
368 /*
369 * Xscale must not have PMD bit 4 set for section mappings.
370 */
371 if (cpu_is_xscale())
372 for (i = 0; i < ARRAY_SIZE(mem_types); i++)
373 mem_types[i].prot_sect &= ~PMD_BIT4;
374
375 /*
376 * ARMv5 and lower, excluding Xscale, bit 4 must be set for
377 * page tables.
378 */
379 if (cpu_arch < CPU_ARCH_ARMv6 && !cpu_is_xscale())
380 for (i = 0; i < ARRAY_SIZE(mem_types); i++)
381 if (mem_types[i].prot_l1)
382 mem_types[i].prot_l1 |= PMD_BIT4;
383
384 cp = &cache_policies[cachepolicy];
385 kern_pgprot = user_pgprot = cp->pte;
386
387 /*
388 * Enable CPU-specific coherency if supported.
389 * (Only available on XSC3 at the moment.)
390 */
391 if (arch_is_coherent()) {
392 if (cpu_is_xsc3()) {
393 mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
394 mem_types[MT_MEMORY].prot_pte |= L_PTE_COHERENT;
395 }
396 }
397
398 /*
399 * ARMv6 and above have extended page tables.
400 */
401 if (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP)) {
402 /*
403 * bit 4 becomes XN which we must clear for the
404 * kernel memory mapping.
405 */
406 mem_types[MT_MEMORY].prot_sect &= ~PMD_SECT_XN;
407 mem_types[MT_ROM].prot_sect &= ~PMD_SECT_XN;
408
409 /*
410 * Mark cache clean areas and XIP ROM read only
411 * from SVC mode and no access from userspace.
412 */
413 mem_types[MT_ROM].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
414 mem_types[MT_MINICLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
415 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
416
417 /*
418 * Mark the device area as "shared device"
419 */
420 mem_types[MT_DEVICE].prot_pte |= L_PTE_BUFFERABLE;
421 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_BUFFERED;
422
423 /*
424 * User pages need to be mapped with the ASID
425 * (iow, non-global)
426 */
427 user_pgprot |= L_PTE_ASID;
428
429#ifdef CONFIG_SMP
430 /*
431 * Mark memory with the "shared" attribute for SMP systems
432 */
433 user_pgprot |= L_PTE_SHARED;
434 kern_pgprot |= L_PTE_SHARED;
435 mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
436#endif
437 }
438
439 for (i = 0; i < 16; i++) {
440 unsigned long v = pgprot_val(protection_map[i]);
441 v = (v & ~(L_PTE_BUFFERABLE|L_PTE_CACHEABLE)) | user_pgprot;
442 protection_map[i] = __pgprot(v);
443 }
444
445 mem_types[MT_LOW_VECTORS].prot_pte |= kern_pgprot;
446 mem_types[MT_HIGH_VECTORS].prot_pte |= kern_pgprot;
447
448 if (cpu_arch >= CPU_ARCH_ARMv5) {
449#ifndef CONFIG_SMP
450 /*
451 * Only use write-through for non-SMP systems
452 */
453 mem_types[MT_LOW_VECTORS].prot_pte &= ~L_PTE_BUFFERABLE;
454 mem_types[MT_HIGH_VECTORS].prot_pte &= ~L_PTE_BUFFERABLE;
455#endif
456 } else {
457 mem_types[MT_MINICLEAN].prot_sect &= ~PMD_SECT_TEX(1);
458 }
459
460 pgprot_kernel = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG |
461 L_PTE_DIRTY | L_PTE_WRITE |
462 L_PTE_EXEC | kern_pgprot);
463
464 mem_types[MT_LOW_VECTORS].prot_l1 |= ecc_mask;
465 mem_types[MT_HIGH_VECTORS].prot_l1 |= ecc_mask;
466 mem_types[MT_MEMORY].prot_sect |= ecc_mask | cp->pmd;
467 mem_types[MT_ROM].prot_sect |= cp->pmd;
468
469 switch (cp->pmd) {
470 case PMD_SECT_WT:
471 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WT;
472 break;
473 case PMD_SECT_WB:
474 case PMD_SECT_WBWA:
475 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WB;
476 break;
477 }
478 printk("Memory policy: ECC %sabled, Data cache %s\n",
479 ecc_mask ? "en" : "dis", cp->policy);
480}
481
482#define vectors_base() (vectors_high() ? 0xffff0000 : 0)
483
484/*
485 * Create the page directory entries and any necessary
486 * page tables for the mapping specified by `md'. We
487 * are able to cope here with varying sizes and address
488 * offsets, and we take full advantage of sections and
489 * supersections.
490 */
491void __init create_mapping(struct map_desc *md)
492{
493 unsigned long virt, length;
494 int prot_sect, prot_l1, domain;
495 pgprot_t prot_pte;
496 unsigned long off = (u32)__pfn_to_phys(md->pfn);
497
498 if (md->virtual != vectors_base() && md->virtual < TASK_SIZE) {
499 printk(KERN_WARNING "BUG: not creating mapping for "
500 "0x%08llx at 0x%08lx in user region\n",
501 __pfn_to_phys((u64)md->pfn), md->virtual);
502 return;
503 }
504
505 if ((md->type == MT_DEVICE || md->type == MT_ROM) &&
506 md->virtual >= PAGE_OFFSET && md->virtual < VMALLOC_END) {
507 printk(KERN_WARNING "BUG: mapping for 0x%08llx at 0x%08lx "
508 "overlaps vmalloc space\n",
509 __pfn_to_phys((u64)md->pfn), md->virtual);
510 }
511
512 domain = mem_types[md->type].domain;
513 prot_pte = __pgprot(mem_types[md->type].prot_pte);
514 prot_l1 = mem_types[md->type].prot_l1 | PMD_DOMAIN(domain);
515 prot_sect = mem_types[md->type].prot_sect | PMD_DOMAIN(domain);
516
517 /*
518 * Catch 36-bit addresses
519 */
520 if(md->pfn >= 0x100000) {
521 if(domain) {
522 printk(KERN_ERR "MM: invalid domain in supersection "
523 "mapping for 0x%08llx at 0x%08lx\n",
524 __pfn_to_phys((u64)md->pfn), md->virtual);
525 return;
526 }
527 if((md->virtual | md->length | __pfn_to_phys(md->pfn))
528 & ~SUPERSECTION_MASK) {
529 printk(KERN_ERR "MM: cannot create mapping for "
530 "0x%08llx at 0x%08lx invalid alignment\n",
531 __pfn_to_phys((u64)md->pfn), md->virtual);
532 return;
533 }
534
535 /*
536 * Shift bits [35:32] of address into bits [23:20] of PMD
537 * (See ARMv6 spec).
538 */
539 off |= (((md->pfn >> (32 - PAGE_SHIFT)) & 0xF) << 20);
540 }
541
542 virt = md->virtual;
543 off -= virt;
544 length = md->length;
545
546 if (mem_types[md->type].prot_l1 == 0 &&
547 (virt & 0xfffff || (virt + off) & 0xfffff || (virt + length) & 0xfffff)) {
548 printk(KERN_WARNING "BUG: map for 0x%08lx at 0x%08lx can not "
549 "be mapped using pages, ignoring.\n",
550 __pfn_to_phys(md->pfn), md->virtual);
551 return;
552 }
553
554 while ((virt & 0xfffff || (virt + off) & 0xfffff) && length >= PAGE_SIZE) {
555 alloc_init_page(virt, virt + off, prot_l1, prot_pte);
556
557 virt += PAGE_SIZE;
558 length -= PAGE_SIZE;
559 }
560
561 /* N.B. ARMv6 supersections are only defined to work with domain 0.
562 * Since domain assignments can in fact be arbitrary, the
563 * 'domain == 0' check below is required to insure that ARMv6
564 * supersections are only allocated for domain 0 regardless
565 * of the actual domain assignments in use.
566 */
567 if ((cpu_architecture() >= CPU_ARCH_ARMv6 || cpu_is_xsc3())
568 && domain == 0) {
569 /*
570 * Align to supersection boundary if !high pages.
571 * High pages have already been checked for proper
572 * alignment above and they will fail the SUPSERSECTION_MASK
573 * check because of the way the address is encoded into
574 * offset.
575 */
576 if (md->pfn <= 0x100000) {
577 while ((virt & ~SUPERSECTION_MASK ||
578 (virt + off) & ~SUPERSECTION_MASK) &&
579 length >= (PGDIR_SIZE / 2)) {
580 alloc_init_section(virt, virt + off, prot_sect);
581
582 virt += (PGDIR_SIZE / 2);
583 length -= (PGDIR_SIZE / 2);
584 }
585 }
586
587 while (length >= SUPERSECTION_SIZE) {
588 alloc_init_supersection(virt, virt + off, prot_sect);
589
590 virt += SUPERSECTION_SIZE;
591 length -= SUPERSECTION_SIZE;
592 }
593 }
594
595 /*
596 * A section mapping covers half a "pgdir" entry.
597 */
598 while (length >= (PGDIR_SIZE / 2)) {
599 alloc_init_section(virt, virt + off, prot_sect);
600
601 virt += (PGDIR_SIZE / 2);
602 length -= (PGDIR_SIZE / 2);
603 }
604
605 while (length >= PAGE_SIZE) {
606 alloc_init_page(virt, virt + off, prot_l1, prot_pte);
607
608 virt += PAGE_SIZE;
609 length -= PAGE_SIZE;
610 }
611}
612
613/*
614 * In order to soft-boot, we need to insert a 1:1 mapping in place of
615 * the user-mode pages. This will then ensure that we have predictable
616 * results when turning the mmu off
617 */
618void setup_mm_for_reboot(char mode)
619{
620 unsigned long base_pmdval;
621 pgd_t *pgd;
622 int i;
623
624 if (current->mm && current->mm->pgd)
625 pgd = current->mm->pgd;
626 else
627 pgd = init_mm.pgd;
628
629 base_pmdval = PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | PMD_TYPE_SECT;
630 if (cpu_architecture() <= CPU_ARCH_ARMv5TEJ && !cpu_is_xscale())
631 base_pmdval |= PMD_BIT4;
632
633 for (i = 0; i < FIRST_USER_PGD_NR + USER_PTRS_PER_PGD; i++, pgd++) {
634 unsigned long pmdval = (i << PGDIR_SHIFT) | base_pmdval;
635 pmd_t *pmd;
636
637 pmd = pmd_off(pgd, i << PGDIR_SHIFT);
638 pmd[0] = __pmd(pmdval);
639 pmd[1] = __pmd(pmdval + (1 << (PGDIR_SHIFT - 1)));
640 flush_pmd_entry(pmd);
641 }
642}
643
644/*
645 * Create the architecture specific mappings
646 */
647void __init iotable_init(struct map_desc *io_desc, int nr)
648{
649 int i;
650
651 for (i = 0; i < nr; i++)
652 create_mapping(io_desc + i);
653}
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