diff options
author | Catalin Marinas <catalin.marinas@arm.com> | 2011-11-22 12:30:29 -0500 |
---|---|---|
committer | Catalin Marinas <catalin.marinas@arm.com> | 2011-12-08 05:30:39 -0500 |
commit | da02877987e6e173ebba137d4e1e155e1f1151cd (patch) | |
tree | 8035bb1fb7def068ed2fd13d5d11ec5857c7d338 /arch/arm/mm/ioremap.c | |
parent | dcfdae04bd92e8a2ea155db0e21e3bddc09e0a89 (diff) |
ARM: LPAE: Page table maintenance for the 3-level format
This patch modifies the pgd/pmd/pte manipulation functions to support
the 3-level page table format. Since there is no need for an 'ext'
argument to cpu_set_pte_ext(), this patch conditionally defines a
different prototype for this function when CONFIG_ARM_LPAE.
The patch also introduces the L_PGD_SWAPPER flag to mark pgd entries
pointing to pmd tables pre-allocated in the swapper_pg_dir and avoid
trying to free them at run-time. This flag is 0 with the classic page
table format.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'arch/arm/mm/ioremap.c')
-rw-r--r-- | arch/arm/mm/ioremap.c | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/arch/arm/mm/ioremap.c b/arch/arm/mm/ioremap.c index c3fa40da3b75..d1f78bacb015 100644 --- a/arch/arm/mm/ioremap.c +++ b/arch/arm/mm/ioremap.c | |||
@@ -64,7 +64,7 @@ void __check_kvm_seq(struct mm_struct *mm) | |||
64 | } while (seq != init_mm.context.kvm_seq); | 64 | } while (seq != init_mm.context.kvm_seq); |
65 | } | 65 | } |
66 | 66 | ||
67 | #ifndef CONFIG_SMP | 67 | #if !defined(CONFIG_SMP) && !defined(CONFIG_ARM_LPAE) |
68 | /* | 68 | /* |
69 | * Section support is unsafe on SMP - If you iounmap and ioremap a region, | 69 | * Section support is unsafe on SMP - If you iounmap and ioremap a region, |
70 | * the other CPUs will not see this change until their next context switch. | 70 | * the other CPUs will not see this change until their next context switch. |
@@ -202,11 +202,13 @@ void __iomem * __arm_ioremap_pfn_caller(unsigned long pfn, | |||
202 | unsigned long addr; | 202 | unsigned long addr; |
203 | struct vm_struct * area; | 203 | struct vm_struct * area; |
204 | 204 | ||
205 | #ifndef CONFIG_ARM_LPAE | ||
205 | /* | 206 | /* |
206 | * High mappings must be supersection aligned | 207 | * High mappings must be supersection aligned |
207 | */ | 208 | */ |
208 | if (pfn >= 0x100000 && (__pfn_to_phys(pfn) & ~SUPERSECTION_MASK)) | 209 | if (pfn >= 0x100000 && (__pfn_to_phys(pfn) & ~SUPERSECTION_MASK)) |
209 | return NULL; | 210 | return NULL; |
211 | #endif | ||
210 | 212 | ||
211 | /* | 213 | /* |
212 | * Don't allow RAM to be mapped - this causes problems with ARMv6+ | 214 | * Don't allow RAM to be mapped - this causes problems with ARMv6+ |
@@ -228,7 +230,7 @@ void __iomem * __arm_ioremap_pfn_caller(unsigned long pfn, | |||
228 | return NULL; | 230 | return NULL; |
229 | addr = (unsigned long)area->addr; | 231 | addr = (unsigned long)area->addr; |
230 | 232 | ||
231 | #ifndef CONFIG_SMP | 233 | #if !defined(CONFIG_SMP) && !defined(CONFIG_ARM_LPAE) |
232 | if (DOMAIN_IO == 0 && | 234 | if (DOMAIN_IO == 0 && |
233 | (((cpu_architecture() >= CPU_ARCH_ARMv6) && (get_cr() & CR_XP)) || | 235 | (((cpu_architecture() >= CPU_ARCH_ARMv6) && (get_cr() & CR_XP)) || |
234 | cpu_is_xsc3()) && pfn >= 0x100000 && | 236 | cpu_is_xsc3()) && pfn >= 0x100000 && |
@@ -320,7 +322,7 @@ __arm_ioremap_exec(unsigned long phys_addr, size_t size, bool cached) | |||
320 | void __iounmap(volatile void __iomem *io_addr) | 322 | void __iounmap(volatile void __iomem *io_addr) |
321 | { | 323 | { |
322 | void *addr = (void *)(PAGE_MASK & (unsigned long)io_addr); | 324 | void *addr = (void *)(PAGE_MASK & (unsigned long)io_addr); |
323 | #ifndef CONFIG_SMP | 325 | #if !defined(CONFIG_SMP) && !defined(CONFIG_ARM_LPAE) |
324 | struct vm_struct **p, *tmp; | 326 | struct vm_struct **p, *tmp; |
325 | 327 | ||
326 | /* | 328 | /* |