aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm/mm/flush.c
diff options
context:
space:
mode:
authorCatalin Marinas <catalin.marinas@arm.com>2005-09-30 11:07:04 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2005-09-30 11:07:04 -0400
commit481467d6fa4489aa42321a067e78bad26349488f (patch)
tree8d6d8335a98d57e204cd5bacc99569ff7d424cae /arch/arm/mm/flush.c
parentdce79affd5d04e9cbabe35016eda55213b9b36f6 (diff)
[ARM] 2939/1: Fix compilation error in arch/arm/mm/flush.c
Patch from Catalin Marinas When CONFIG_CPU_CACHE_VIPT is defined, the flush_pfn_alias() function is implicitely declared and it later conflicts with its actual definition. This patch moves the function definition to the beginning of the file. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mm/flush.c')
-rw-r--r--arch/arm/mm/flush.c36
1 files changed, 18 insertions, 18 deletions
diff --git a/arch/arm/mm/flush.c b/arch/arm/mm/flush.c
index b0208c992576..c9a03981b785 100644
--- a/arch/arm/mm/flush.c
+++ b/arch/arm/mm/flush.c
@@ -17,6 +17,24 @@
17 17
18#ifdef CONFIG_CPU_CACHE_VIPT 18#ifdef CONFIG_CPU_CACHE_VIPT
19 19
20#define ALIAS_FLUSH_START 0xffff4000
21
22#define TOP_PTE(x) pte_offset_kernel(top_pmd, x)
23
24static void flush_pfn_alias(unsigned long pfn, unsigned long vaddr)
25{
26 unsigned long to = ALIAS_FLUSH_START + (CACHE_COLOUR(vaddr) << PAGE_SHIFT);
27
28 set_pte(TOP_PTE(to), pfn_pte(pfn, PAGE_KERNEL));
29 flush_tlb_kernel_page(to);
30
31 asm( "mcrr p15, 0, %1, %0, c14\n"
32 " mcrr p15, 0, %1, %0, c5\n"
33 :
34 : "r" (to), "r" (to + PAGE_SIZE - L1_CACHE_BYTES)
35 : "cc");
36}
37
20void flush_cache_mm(struct mm_struct *mm) 38void flush_cache_mm(struct mm_struct *mm)
21{ 39{
22 if (cache_is_vivt()) { 40 if (cache_is_vivt()) {
@@ -67,24 +85,6 @@ void flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr, unsig
67 if (cache_is_vipt_aliasing()) 85 if (cache_is_vipt_aliasing())
68 flush_pfn_alias(pfn, user_addr); 86 flush_pfn_alias(pfn, user_addr);
69} 87}
70
71#define ALIAS_FLUSH_START 0xffff4000
72
73#define TOP_PTE(x) pte_offset_kernel(top_pmd, x)
74
75static void flush_pfn_alias(unsigned long pfn, unsigned long vaddr)
76{
77 unsigned long to = ALIAS_FLUSH_START + (CACHE_COLOUR(vaddr) << PAGE_SHIFT);
78
79 set_pte(TOP_PTE(to), pfn_pte(pfn, PAGE_KERNEL));
80 flush_tlb_kernel_page(to);
81
82 asm( "mcrr p15, 0, %1, %0, c14\n"
83 " mcrr p15, 0, %1, %0, c5\n"
84 :
85 : "r" (to), "r" (to + PAGE_SIZE - L1_CACHE_BYTES)
86 : "cc");
87}
88#else 88#else
89#define flush_pfn_alias(pfn,vaddr) do { } while (0) 89#define flush_pfn_alias(pfn,vaddr) do { } while (0)
90#endif 90#endif