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authorRussell King <rmk+kernel@arm.linux.org.uk>2011-07-02 10:20:44 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2012-01-26 15:06:28 -0500
commit67ece1443174d852e71c42facb3e2d7dd338c88a (patch)
tree418359d432acfcb2ecc4c58c8afa5f73de4fa01e /arch/arm/mm/flush.c
parent6e78df176141f2cb673bed7fa47825e3c6a8719f (diff)
ARM: pgtable: consolidate set_pte_ext(TOP_PTE,...) + tlb flush
A number of places establish a PTE in our top page table and immediately flush the TLB. Rather than having this at every callsite, provide an inline function for this purpose. This changes some global tlb flushes to be local; each time we setup one of these mappings, we always do it with preemption disabled which would prevent us migrating to another CPU. Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mm/flush.c')
-rw-r--r--arch/arm/mm/flush.c10
1 files changed, 4 insertions, 6 deletions
diff --git a/arch/arm/mm/flush.c b/arch/arm/mm/flush.c
index f4d407af4690..4d0b70f035eb 100644
--- a/arch/arm/mm/flush.c
+++ b/arch/arm/mm/flush.c
@@ -28,8 +28,7 @@ static void flush_pfn_alias(unsigned long pfn, unsigned long vaddr)
28 unsigned long to = FLUSH_ALIAS_START + (CACHE_COLOUR(vaddr) << PAGE_SHIFT); 28 unsigned long to = FLUSH_ALIAS_START + (CACHE_COLOUR(vaddr) << PAGE_SHIFT);
29 const int zero = 0; 29 const int zero = 0;
30 30
31 set_pte_ext(TOP_PTE(to), pfn_pte(pfn, PAGE_KERNEL), 0); 31 set_top_pte(to, pfn_pte(pfn, PAGE_KERNEL));
32 flush_tlb_kernel_page(to);
33 32
34 asm( "mcrr p15, 0, %1, %0, c14\n" 33 asm( "mcrr p15, 0, %1, %0, c14\n"
35 " mcr p15, 0, %2, c7, c10, 4" 34 " mcr p15, 0, %2, c7, c10, 4"
@@ -40,13 +39,12 @@ static void flush_pfn_alias(unsigned long pfn, unsigned long vaddr)
40 39
41static void flush_icache_alias(unsigned long pfn, unsigned long vaddr, unsigned long len) 40static void flush_icache_alias(unsigned long pfn, unsigned long vaddr, unsigned long len)
42{ 41{
43 unsigned long colour = CACHE_COLOUR(vaddr); 42 unsigned long va = FLUSH_ALIAS_START + (CACHE_COLOUR(vaddr) << PAGE_SHIFT);
44 unsigned long offset = vaddr & (PAGE_SIZE - 1); 43 unsigned long offset = vaddr & (PAGE_SIZE - 1);
45 unsigned long to; 44 unsigned long to;
46 45
47 set_pte_ext(TOP_PTE(FLUSH_ALIAS_START) + colour, pfn_pte(pfn, PAGE_KERNEL), 0); 46 set_top_pte(va, pfn_pte(pfn, PAGE_KERNEL));
48 to = FLUSH_ALIAS_START + (colour << PAGE_SHIFT) + offset; 47 to = va + offset;
49 flush_tlb_kernel_page(to);
50 flush_icache_range(to, to + len); 48 flush_icache_range(to, to + len);
51} 49}
52 50