[ARM] fix a couple clear_user_highpage assembly constraints

In all cases the kaddr is assigned an input register even though it is
modified in the assembly code.  Let's assign a new variable to the
modified value and mark those inline asm with volatile otherwise they
get optimized away because the output variable is otherwise not used.

Also fix a few conversion errors in copypage-feroceon.c and
copypage-v4mc.c.

Signed-off-by: Nicolas Pitre <nico@marvell.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

1 files changed, 5 insertions, 5 deletions

diff --git a/arch/arm/mm/copypage-v4wt.c b/arch/arm/mm/copypage-v4wt.c
index b8a345d6e77e..0f1188efae45 100644
--- a/arch/arm/mm/copypage-v4wt.c
+++ b/arch/arm/mm/copypage-v4wt.c
@@ -62,9 +62,9 @@ void v4wt_copy_user_highpage(struct page *to, struct page *from,
  */
 void v4wt_clear_user_highpage(struct page *page, unsigned long vaddr)
 {
-        void *kaddr = kmap_atomic(page, KM_USER0);
-        asm("\
-        mov     r1, %1                          @ 1\n\
+        void *ptr, *kaddr = kmap_atomic(page, KM_USER0);
+        asm volatile("\
+        mov     r1, %2                          @ 1\n\
         mov     r2, #0                          @ 1\n\
         mov     r3, #0                          @ 1\n\
         mov     ip, #0                          @ 1\n\
@@ -76,8 +76,8 @@ void v4wt_clear_user_highpage(struct page *page, unsigned long vaddr)
         subs    r1, r1, #1                      @ 1\n\
         bne     1b                              @ 1\n\
         mcr     p15, 0, r2, c7, c7, 0           @ flush ID cache"
-        :
-        : "r" (kaddr), "I" (PAGE_SIZE / 64)
+        : "=r" (ptr)
+        : "0" (kaddr), "I" (PAGE_SIZE / 64)
         : "r1", "r2", "r3", "ip", "lr");
         kunmap_atomic(kaddr, KM_USER0);
 }