diff options
author | Russell King <rmk@dyn-67.arm.linux.org.uk> | 2008-10-31 09:08:02 -0400 |
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committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2008-11-27 18:53:46 -0500 |
commit | d73e60b7144a86baf0fdfcc9537a70bb4f72e11c (patch) | |
tree | 02155154caf6f1a5d6ce38f2a89ed67f875c7791 /arch/arm/mm/copypage-v4wt.S | |
parent | 487ff32082a9bd7489d8185cf7d7a2fdf18a22fa (diff) |
[ARM] copypage: convert assembly files to C
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mm/copypage-v4wt.S')
-rw-r--r-- | arch/arm/mm/copypage-v4wt.S | 73 |
1 files changed, 0 insertions, 73 deletions
diff --git a/arch/arm/mm/copypage-v4wt.S b/arch/arm/mm/copypage-v4wt.S deleted file mode 100644 index e1f2af28d549..000000000000 --- a/arch/arm/mm/copypage-v4wt.S +++ /dev/null | |||
@@ -1,73 +0,0 @@ | |||
1 | /* | ||
2 | * linux/arch/arm/lib/copypage-v4.S | ||
3 | * | ||
4 | * Copyright (C) 1995-1999 Russell King | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | * | ||
10 | * ASM optimised string functions | ||
11 | * | ||
12 | * This is for CPUs with a writethrough cache and 'flush ID cache' is | ||
13 | * the only supported cache operation. | ||
14 | */ | ||
15 | #include <linux/linkage.h> | ||
16 | #include <linux/init.h> | ||
17 | #include <asm/asm-offsets.h> | ||
18 | |||
19 | .text | ||
20 | .align 5 | ||
21 | /* | ||
22 | * ARMv4 optimised copy_user_page | ||
23 | * | ||
24 | * Since we have writethrough caches, we don't have to worry about | ||
25 | * dirty data in the cache. However, we do have to ensure that | ||
26 | * subsequent reads are up to date. | ||
27 | */ | ||
28 | ENTRY(v4wt_copy_user_page) | ||
29 | stmfd sp!, {r4, lr} @ 2 | ||
30 | mov r2, #PAGE_SZ/64 @ 1 | ||
31 | ldmia r1!, {r3, r4, ip, lr} @ 4 | ||
32 | 1: stmia r0!, {r3, r4, ip, lr} @ 4 | ||
33 | ldmia r1!, {r3, r4, ip, lr} @ 4+1 | ||
34 | stmia r0!, {r3, r4, ip, lr} @ 4 | ||
35 | ldmia r1!, {r3, r4, ip, lr} @ 4 | ||
36 | stmia r0!, {r3, r4, ip, lr} @ 4 | ||
37 | ldmia r1!, {r3, r4, ip, lr} @ 4 | ||
38 | subs r2, r2, #1 @ 1 | ||
39 | stmia r0!, {r3, r4, ip, lr} @ 4 | ||
40 | ldmneia r1!, {r3, r4, ip, lr} @ 4 | ||
41 | bne 1b @ 1 | ||
42 | mcr p15, 0, r2, c7, c7, 0 @ flush ID cache | ||
43 | ldmfd sp!, {r4, pc} @ 3 | ||
44 | |||
45 | .align 5 | ||
46 | /* | ||
47 | * ARMv4 optimised clear_user_page | ||
48 | * | ||
49 | * Same story as above. | ||
50 | */ | ||
51 | ENTRY(v4wt_clear_user_page) | ||
52 | str lr, [sp, #-4]! | ||
53 | mov r1, #PAGE_SZ/64 @ 1 | ||
54 | mov r2, #0 @ 1 | ||
55 | mov r3, #0 @ 1 | ||
56 | mov ip, #0 @ 1 | ||
57 | mov lr, #0 @ 1 | ||
58 | 1: stmia r0!, {r2, r3, ip, lr} @ 4 | ||
59 | stmia r0!, {r2, r3, ip, lr} @ 4 | ||
60 | stmia r0!, {r2, r3, ip, lr} @ 4 | ||
61 | stmia r0!, {r2, r3, ip, lr} @ 4 | ||
62 | subs r1, r1, #1 @ 1 | ||
63 | bne 1b @ 1 | ||
64 | mcr p15, 0, r2, c7, c7, 0 @ flush ID cache | ||
65 | ldr pc, [sp], #4 | ||
66 | |||
67 | __INITDATA | ||
68 | |||
69 | .type v4wt_user_fns, #object | ||
70 | ENTRY(v4wt_user_fns) | ||
71 | .long v4wt_clear_user_page | ||
72 | .long v4wt_copy_user_page | ||
73 | .size v4wt_user_fns, . - v4wt_user_fns | ||