ARM: Fix errata 411920 workarounds

Errata 411920 indicates that any "invalidate entire instruction cache"
operation can fail if the right conditions are present.  This is not
limited just to those operations in flush.c, but elsewhere.  Place the
workaround in the already existing __flush_icache_all() function
instead.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

1 files changed, 1 insertions, 4 deletions

diff --git a/arch/arm/mm/context.c b/arch/arm/mm/context.c
index 6bda76a43199..a9e22e31eaa1 100644
--- a/arch/arm/mm/context.c
+++ b/arch/arm/mm/context.c
@@ -50,10 +50,7 @@ void __new_context(struct mm_struct *mm)
                 isb();
                 flush_tlb_all();
                 if (icache_is_vivt_asid_tagged()) {
-                        asm("mcr        p15, 0, %0, c7, c5, 0   @ invalidate I-cache\n"
-                            "mcr        p15, 0, %0, c7, c5, 6   @ flush BTAC/BTB\n"
-                            :
-                            : "r" (0));
+                        __flush_icache_all();
                         dsb();
                 }
         }