ARM: dma-mapping: fix for speculative prefetching

ARMv6 and ARMv7 CPUs can perform speculative prefetching, which makes
DMA cache coherency handling slightly more interesting.  Rather than
being able to rely upon the CPU not accessing the DMA buffer until DMA
has completed, we now must expect that the cache could be loaded with
possibly stale data from the DMA buffer.

Where DMA involves data being transferred to the device, we clean the
cache before handing it over for DMA, otherwise we invalidate the buffer
to get rid of potential writebacks.  On DMA Completion, if data was
transferred from the device, we invalidate the buffer to get rid of
any stale speculative prefetches.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Tested-By: Santosh Shilimkar <santosh.shilimkar@ti.com>

1 files changed, 6 insertions, 4 deletions

diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S
index b1cd0fd91207..bcd64f265870 100644
--- a/arch/arm/mm/cache-v7.S
+++ b/arch/arm/mm/cache-v7.S
@@ -279,10 +279,9 @@ ENDPROC(v7_dma_flush_range)
  */
 ENTRY(v7_dma_map_area)
         add     r1, r1, r0
-        cmp     r2, #DMA_TO_DEVICE
-        beq     v7_dma_clean_range
-        bcs     v7_dma_inv_range
-        b       v7_dma_flush_range
+        teq     r2, #DMA_FROM_DEVICE
+        beq     v7_dma_inv_range
+        b       v7_dma_clean_range
 ENDPROC(v7_dma_map_area)
 
 /*
@@ -292,6 +291,9 @@ ENDPROC(v7_dma_map_area)
  *      - dir   - DMA direction
  */
 ENTRY(v7_dma_unmap_area)
+        add     r1, r1, r0
+        teq     r2, #DMA_TO_DEVICE
+        bne     v7_dma_inv_range
         mov     pc, lr
 ENDPROC(v7_dma_unmap_area)