aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm/mm/cache-v7.S
diff options
context:
space:
mode:
authorCatalin Marinas <catalin.marinas@arm.com>2008-08-28 06:22:32 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2008-09-01 07:06:34 -0400
commit93ed3970114983543bbebd195bef65db84444ea2 (patch)
tree9df88b61a2a7b3cc493c6cfc5f4848448250f6b5 /arch/arm/mm/cache-v7.S
parent8d5796d2ec6b5a4e7a52861144e63af438d6f8f7 (diff)
[ARM] 5227/1: Add the ENDPROC declarations to the .S files
This declaration specifies the "function" type and size for various assembly functions, mainly needed for generating the correct branch instructions in Thumb-2. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mm/cache-v7.S')
-rw-r--r--arch/arm/mm/cache-v7.S10
1 files changed, 10 insertions, 0 deletions
diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S
index 35ffc4d95997..d19c2bec2b1f 100644
--- a/arch/arm/mm/cache-v7.S
+++ b/arch/arm/mm/cache-v7.S
@@ -66,6 +66,7 @@ finished:
66 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr 66 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
67 isb 67 isb
68 mov pc, lr 68 mov pc, lr
69ENDPROC(v7_flush_dcache_all)
69 70
70/* 71/*
71 * v7_flush_cache_all() 72 * v7_flush_cache_all()
@@ -85,6 +86,7 @@ ENTRY(v7_flush_kern_cache_all)
85 mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate 86 mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate
86 ldmfd sp!, {r4-r5, r7, r9-r11, lr} 87 ldmfd sp!, {r4-r5, r7, r9-r11, lr}
87 mov pc, lr 88 mov pc, lr
89ENDPROC(v7_flush_kern_cache_all)
88 90
89/* 91/*
90 * v7_flush_cache_all() 92 * v7_flush_cache_all()
@@ -110,6 +112,8 @@ ENTRY(v7_flush_user_cache_all)
110 */ 112 */
111ENTRY(v7_flush_user_cache_range) 113ENTRY(v7_flush_user_cache_range)
112 mov pc, lr 114 mov pc, lr
115ENDPROC(v7_flush_user_cache_all)
116ENDPROC(v7_flush_user_cache_range)
113 117
114/* 118/*
115 * v7_coherent_kern_range(start,end) 119 * v7_coherent_kern_range(start,end)
@@ -155,6 +159,8 @@ ENTRY(v7_coherent_user_range)
155 dsb 159 dsb
156 isb 160 isb
157 mov pc, lr 161 mov pc, lr
162ENDPROC(v7_coherent_kern_range)
163ENDPROC(v7_coherent_user_range)
158 164
159/* 165/*
160 * v7_flush_kern_dcache_page(kaddr) 166 * v7_flush_kern_dcache_page(kaddr)
@@ -174,6 +180,7 @@ ENTRY(v7_flush_kern_dcache_page)
174 blo 1b 180 blo 1b
175 dsb 181 dsb
176 mov pc, lr 182 mov pc, lr
183ENDPROC(v7_flush_kern_dcache_page)
177 184
178/* 185/*
179 * v7_dma_inv_range(start,end) 186 * v7_dma_inv_range(start,end)
@@ -202,6 +209,7 @@ ENTRY(v7_dma_inv_range)
202 blo 1b 209 blo 1b
203 dsb 210 dsb
204 mov pc, lr 211 mov pc, lr
212ENDPROC(v7_dma_inv_range)
205 213
206/* 214/*
207 * v7_dma_clean_range(start,end) 215 * v7_dma_clean_range(start,end)
@@ -219,6 +227,7 @@ ENTRY(v7_dma_clean_range)
219 blo 1b 227 blo 1b
220 dsb 228 dsb
221 mov pc, lr 229 mov pc, lr
230ENDPROC(v7_dma_clean_range)
222 231
223/* 232/*
224 * v7_dma_flush_range(start,end) 233 * v7_dma_flush_range(start,end)
@@ -236,6 +245,7 @@ ENTRY(v7_dma_flush_range)
236 blo 1b 245 blo 1b
237 dsb 246 dsb
238 mov pc, lr 247 mov pc, lr
248ENDPROC(v7_dma_flush_range)
239 249
240 __INITDATA 250 __INITDATA
241 251