Merge branch 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm

* 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm: (236 commits)
  [ARM] 5300/1: fixup spitz reset during boot
  [ARM] 5295/1: make ZONE_DMA optional
  [ARM] 5239/1: Palm Zire 72 power management support
  [ARM] 5298/1: Drop desc_handle_irq()
  [ARM] 5297/1: [KS8695] Fix two compile-time warnings
  [ARM] 5296/1: [KS8695] Replace macro's with trailing underscores.
  [ARM] pxa: allow multi-machine PCMCIA builds
  [ARM] pxa: add preliminary CPUFREQ support for PXA3xx
  [ARM] pxa: add missing ACCR bit definitions to pxa3xx-regs.h
  [ARM] pxa: rename cpu-pxa.c to cpufreq-pxa2xx.c
  [ARM] pxa/zylonite: add support for USB OHCI
  [ARM] ohci-pxa27x: use ioremap() and offset for register access
  [ARM] ohci-pxa27x: introduce pxa27x_clear_otgph()
  [ARM] ohci-pxa27x: use platform_get_{irq,resource} for the resource
  [ARM] ohci-pxa27x: move OHCI controller specific registers into the driver
  [ARM] ohci-pxa27x: introduce flags to avoid direct access to OHCI registers
  [ARM] pxa: move I2S register and bit definitions into pxa2xx-i2s.c
  [ARM] pxa: simplify DMA register definitions
  [ARM] pxa: make additional DCSR bits valid for PXA3xx
  [ARM] pxa: move i2c register and bit definitions into i2c-pxa.c
  ...

Fixed up conflicts in
	arch/arm/mach-versatile/core.c
	sound/soc/pxa/pxa2xx-ac97.c
	sound/soc/pxa/pxa2xx-i2s.c
manually.

1 files changed, 10 insertions, 0 deletions

diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S
index 35ffc4d95997..d19c2bec2b1f 100644
--- a/arch/arm/mm/cache-v7.S
+++ b/arch/arm/mm/cache-v7.S
@@ -66,6 +66,7 @@ finished:
         mcr     p15, 2, r10, c0, c0, 0          @ select current cache level in cssr
         isb
         mov     pc, lr
+ENDPROC(v7_flush_dcache_all)
 
 /*
  *      v7_flush_cache_all()
@@ -85,6 +86,7 @@ ENTRY(v7_flush_kern_cache_all)
         mcr     p15, 0, r0, c7, c5, 0           @ I+BTB cache invalidate
         ldmfd   sp!, {r4-r5, r7, r9-r11, lr}
         mov     pc, lr
+ENDPROC(v7_flush_kern_cache_all)
 
 /*
  *      v7_flush_cache_all()
@@ -110,6 +112,8 @@ ENTRY(v7_flush_user_cache_all)
  */
 ENTRY(v7_flush_user_cache_range)
         mov     pc, lr
+ENDPROC(v7_flush_user_cache_all)
+ENDPROC(v7_flush_user_cache_range)
 
 /*
  *      v7_coherent_kern_range(start,end)
@@ -155,6 +159,8 @@ ENTRY(v7_coherent_user_range)
         dsb
         isb
         mov     pc, lr
+ENDPROC(v7_coherent_kern_range)
+ENDPROC(v7_coherent_user_range)
 
 /*
  *      v7_flush_kern_dcache_page(kaddr)
@@ -174,6 +180,7 @@ ENTRY(v7_flush_kern_dcache_page)
         blo     1b
         dsb
         mov     pc, lr
+ENDPROC(v7_flush_kern_dcache_page)
 
 /*
  *      v7_dma_inv_range(start,end)
@@ -202,6 +209,7 @@ ENTRY(v7_dma_inv_range)
         blo     1b
         dsb
         mov     pc, lr
+ENDPROC(v7_dma_inv_range)
 
 /*
  *      v7_dma_clean_range(start,end)
@@ -219,6 +227,7 @@ ENTRY(v7_dma_clean_range)
         blo     1b
         dsb
         mov     pc, lr
+ENDPROC(v7_dma_clean_range)
 
 /*
  *      v7_dma_flush_range(start,end)
@@ -236,6 +245,7 @@ ENTRY(v7_dma_flush_range)
         blo     1b
         dsb
         mov     pc, lr
+ENDPROC(v7_dma_flush_range)
 
         __INITDATA