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authorCatalin Marinas <catalin.marinas@arm.com>2010-06-21 10:10:07 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2010-07-01 05:12:31 -0400
commitad642d9f58f1af6e96efccb5f84e52c6d01db5c4 (patch)
tree4319ed1e81f50c7035457cc0fa1cf4bcdf760abb /arch/arm/mm/cache-v6.S
parentca57926d53580f7c950496cb7ef6d7930610e1dd (diff)
ARM: 6188/1: Add a config option for the ARM11MPCore DMA cache maintenance workaround
Commit f4d6477f introduced a workaround for the lack of hardware broadcasting of the cache maintenance operations on ARM11MPCore. However, the workaround is only valid on CPUs that do not do speculative loads into the D-cache. This patch adds a Kconfig option with the corresponding help to make the above clear. When the DMA_CACHE_RWFO option is disabled, the kernel behaviour is that prior to the f4d6477f commit. This also allows ARMv6 UP processors with speculative loads to work correctly. For other processors, a different workaround may be needed. Cc: Ronen Shitrit <rshitrit@marvell.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mm/cache-v6.S')
-rw-r--r--arch/arm/mm/cache-v6.S15
1 files changed, 12 insertions, 3 deletions
diff --git a/arch/arm/mm/cache-v6.S b/arch/arm/mm/cache-v6.S
index 332b48c6d4ff..86aa689ef1aa 100644
--- a/arch/arm/mm/cache-v6.S
+++ b/arch/arm/mm/cache-v6.S
@@ -211,7 +211,7 @@ v6_dma_inv_range:
211 mcrne p15, 0, r1, c7, c15, 1 @ clean & invalidate unified line 211 mcrne p15, 0, r1, c7, c15, 1 @ clean & invalidate unified line
212#endif 212#endif
2131: 2131:
214#ifdef CONFIG_SMP 214#ifdef CONFIG_DMA_CACHE_RWFO
215 ldr r2, [r0] @ read for ownership 215 ldr r2, [r0] @ read for ownership
216 str r2, [r0] @ write for ownership 216 str r2, [r0] @ write for ownership
217#endif 217#endif
@@ -235,7 +235,7 @@ v6_dma_inv_range:
235v6_dma_clean_range: 235v6_dma_clean_range:
236 bic r0, r0, #D_CACHE_LINE_SIZE - 1 236 bic r0, r0, #D_CACHE_LINE_SIZE - 1
2371: 2371:
238#ifdef CONFIG_SMP 238#ifdef CONFIG_DMA_CACHE_RWFO
239 ldr r2, [r0] @ read for ownership 239 ldr r2, [r0] @ read for ownership
240#endif 240#endif
241#ifdef HARVARD_CACHE 241#ifdef HARVARD_CACHE
@@ -258,7 +258,7 @@ v6_dma_clean_range:
258ENTRY(v6_dma_flush_range) 258ENTRY(v6_dma_flush_range)
259 bic r0, r0, #D_CACHE_LINE_SIZE - 1 259 bic r0, r0, #D_CACHE_LINE_SIZE - 1
2601: 2601:
261#ifdef CONFIG_SMP 261#ifdef CONFIG_DMA_CACHE_RWFO
262 ldr r2, [r0] @ read for ownership 262 ldr r2, [r0] @ read for ownership
263 str r2, [r0] @ write for ownership 263 str r2, [r0] @ write for ownership
264#endif 264#endif
@@ -284,9 +284,13 @@ ENTRY(v6_dma_map_area)
284 add r1, r1, r0 284 add r1, r1, r0
285 teq r2, #DMA_FROM_DEVICE 285 teq r2, #DMA_FROM_DEVICE
286 beq v6_dma_inv_range 286 beq v6_dma_inv_range
287#ifndef CONFIG_DMA_CACHE_RWFO
288 b v6_dma_clean_range
289#else
287 teq r2, #DMA_TO_DEVICE 290 teq r2, #DMA_TO_DEVICE
288 beq v6_dma_clean_range 291 beq v6_dma_clean_range
289 b v6_dma_flush_range 292 b v6_dma_flush_range
293#endif
290ENDPROC(v6_dma_map_area) 294ENDPROC(v6_dma_map_area)
291 295
292/* 296/*
@@ -296,6 +300,11 @@ ENDPROC(v6_dma_map_area)
296 * - dir - DMA direction 300 * - dir - DMA direction
297 */ 301 */
298ENTRY(v6_dma_unmap_area) 302ENTRY(v6_dma_unmap_area)
303#ifndef CONFIG_DMA_CACHE_RWFO
304 add r1, r1, r0
305 teq r2, #DMA_TO_DEVICE
306 bne v6_dma_inv_range
307#endif
299 mov pc, lr 308 mov pc, lr
300ENDPROC(v6_dma_unmap_area) 309ENDPROC(v6_dma_unmap_area)
301 310