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authorGen FUKATSU <fukatsu.gen@jp.panasonic.com>2005-09-30 11:09:17 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2005-09-30 11:09:17 -0400
commit217874feed0d3a6543a6b7127782f4a08bffd731 (patch)
tree88c9468bea86336ac5cf27fb72252bd3527b7cb3 /arch/arm/mm/cache-v6.S
parenta06f5466c4576dcbf838a50a87903b0082774da7 (diff)
[ARM] 2940/1: Fix BTB entry flush in arch/arm/mm/cache-v6.S
Patch from Gen FUKATSU Invalidate BTB entry instruction flushes two instruction at a time. Therefore this instruction should be done four times after invalidate instruction cache line. Signed-off-by: Gen Fukatsu Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mm/cache-v6.S')
-rw-r--r--arch/arm/mm/cache-v6.S9
1 files changed, 8 insertions, 1 deletions
diff --git a/arch/arm/mm/cache-v6.S b/arch/arm/mm/cache-v6.S
index 85c10a71e7c6..72966d90e956 100644
--- a/arch/arm/mm/cache-v6.S
+++ b/arch/arm/mm/cache-v6.S
@@ -18,6 +18,7 @@
18#define HARVARD_CACHE 18#define HARVARD_CACHE
19#define CACHE_LINE_SIZE 32 19#define CACHE_LINE_SIZE 32
20#define D_CACHE_LINE_SIZE 32 20#define D_CACHE_LINE_SIZE 32
21#define BTB_FLUSH_SIZE 8
21 22
22/* 23/*
23 * v6_flush_cache_all() 24 * v6_flush_cache_all()
@@ -98,7 +99,13 @@ ENTRY(v6_coherent_user_range)
98 mcr p15, 0, r0, c7, c5, 1 @ invalidate I line 99 mcr p15, 0, r0, c7, c5, 1 @ invalidate I line
99#endif 100#endif
100 mcr p15, 0, r0, c7, c5, 7 @ invalidate BTB entry 101 mcr p15, 0, r0, c7, c5, 7 @ invalidate BTB entry
101 add r0, r0, #CACHE_LINE_SIZE 102 add r0, r0, #BTB_FLUSH_SIZE
103 mcr p15, 0, r0, c7, c5, 7 @ invalidate BTB entry
104 add r0, r0, #BTB_FLUSH_SIZE
105 mcr p15, 0, r0, c7, c5, 7 @ invalidate BTB entry
106 add r0, r0, #BTB_FLUSH_SIZE
107 mcr p15, 0, r0, c7, c5, 7 @ invalidate BTB entry
108 add r0, r0, #BTB_FLUSH_SIZE
102 cmp r0, r1 109 cmp r0, r1
103 blo 1b 110 blo 1b
104#ifdef HARVARD_CACHE 111#ifdef HARVARD_CACHE