diff options
author | Catalin Marinas <catalin.marinas@arm.com> | 2009-04-30 12:06:03 -0400 |
---|---|---|
committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2009-04-30 15:12:47 -0400 |
commit | 9cba3ccc8fe77b67aff2db8f5827d7cb752ce11f (patch) | |
tree | cb73cbaa3c197180b7f9d829561121197a8c69db /arch/arm/mm/cache-v6.S | |
parent | 10993374f84cc1c4100aea9eca7fa154518ffc5e (diff) |
[ARM] 5488/1: ARM errata: Invalidation of the Instruction Cache operation can fail
This patch implements the recommended workaround for erratum 411920
(ARM1136, ARM1156, ARM1176).
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mm/cache-v6.S')
-rw-r--r-- | arch/arm/mm/cache-v6.S | 33 |
1 files changed, 33 insertions, 0 deletions
diff --git a/arch/arm/mm/cache-v6.S b/arch/arm/mm/cache-v6.S index 2c6c2a7c05a0..8f5c13f4c936 100644 --- a/arch/arm/mm/cache-v6.S +++ b/arch/arm/mm/cache-v6.S | |||
@@ -20,6 +20,31 @@ | |||
20 | #define D_CACHE_LINE_SIZE 32 | 20 | #define D_CACHE_LINE_SIZE 32 |
21 | #define BTB_FLUSH_SIZE 8 | 21 | #define BTB_FLUSH_SIZE 8 |
22 | 22 | ||
23 | #ifdef CONFIG_ARM_ERRATA_411920 | ||
24 | /* | ||
25 | * Invalidate the entire I cache (this code is a workaround for the ARM1136 | ||
26 | * erratum 411920 - Invalidate Instruction Cache operation can fail. This | ||
27 | * erratum is present in 1136, 1156 and 1176. It does not affect the MPCore. | ||
28 | * | ||
29 | * Registers: | ||
30 | * r0 - set to 0 | ||
31 | * r1 - corrupted | ||
32 | */ | ||
33 | ENTRY(v6_icache_inval_all) | ||
34 | mov r0, #0 | ||
35 | mrs r1, cpsr | ||
36 | cpsid ifa @ disable interrupts | ||
37 | mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache | ||
38 | mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache | ||
39 | mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache | ||
40 | mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache | ||
41 | msr cpsr_cx, r1 @ restore interrupts | ||
42 | .rept 11 @ ARM Ltd recommends at least | ||
43 | nop @ 11 NOPs | ||
44 | .endr | ||
45 | mov pc, lr | ||
46 | #endif | ||
47 | |||
23 | /* | 48 | /* |
24 | * v6_flush_cache_all() | 49 | * v6_flush_cache_all() |
25 | * | 50 | * |
@@ -31,8 +56,12 @@ ENTRY(v6_flush_kern_cache_all) | |||
31 | mov r0, #0 | 56 | mov r0, #0 |
32 | #ifdef HARVARD_CACHE | 57 | #ifdef HARVARD_CACHE |
33 | mcr p15, 0, r0, c7, c14, 0 @ D cache clean+invalidate | 58 | mcr p15, 0, r0, c7, c14, 0 @ D cache clean+invalidate |
59 | #ifndef CONFIG_ARM_ERRATA_411920 | ||
34 | mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate | 60 | mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate |
35 | #else | 61 | #else |
62 | b v6_icache_inval_all | ||
63 | #endif | ||
64 | #else | ||
36 | mcr p15, 0, r0, c7, c15, 0 @ Cache clean+invalidate | 65 | mcr p15, 0, r0, c7, c15, 0 @ Cache clean+invalidate |
37 | #endif | 66 | #endif |
38 | mov pc, lr | 67 | mov pc, lr |
@@ -103,8 +132,12 @@ ENTRY(v6_coherent_user_range) | |||
103 | mov r0, #0 | 132 | mov r0, #0 |
104 | #ifdef HARVARD_CACHE | 133 | #ifdef HARVARD_CACHE |
105 | mcr p15, 0, r0, c7, c10, 4 @ drain write buffer | 134 | mcr p15, 0, r0, c7, c10, 4 @ drain write buffer |
135 | #ifndef CONFIG_ARM_ERRATA_411920 | ||
106 | mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate | 136 | mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate |
107 | #else | 137 | #else |
138 | b v6_icache_inval_all | ||
139 | #endif | ||
140 | #else | ||
108 | mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB | 141 | mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB |
109 | #endif | 142 | #endif |
110 | mov pc, lr | 143 | mov pc, lr |