diff options
author | Linus Torvalds <torvalds@linux-foundation.org> | 2009-12-17 18:53:41 -0500 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2009-12-17 18:53:41 -0500 |
commit | a695bc683609a2b815915e4cfcd93e4ccc0e2cae (patch) | |
tree | 824d6b35783317f929fe13a9efcc8a35d5e00311 /arch/arm/mm/cache-v4wb.S | |
parent | 6485536bcf499839a54dcda8a8d47ea0bd29b375 (diff) | |
parent | 6665398afafcb1c75d933c1452a9010644aba3e6 (diff) |
Merge branch 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm
* 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm:
PCMCIA: fix pxa2xx_lubbock modular build error
[ARM] Update mach-types
[ARM] pxa: fix no reference of cpu_is_pxa25x() in devices.c
[ARM] pxa/cm-x300: add PWM backlight support
revert "[ARM] pxa/cm-x300: add PWM backlight support"
ARM: use flush_kernel_dcache_area() for dmabounce
ARM: add size argument to __cpuc_flush_dcache_page
ARM: 5848/1: kill flush_ioremap_region()
ARM: cache-l2x0: make better use of background cache handling
ARM: cache-l2x0: avoid taking spinlock for every iteration
[ARM] Kirkwood: Add LaCie Network Space v2 support
ARM: dove: fix the mm mmu flags of the pj4 procinfo
Diffstat (limited to 'arch/arm/mm/cache-v4wb.S')
-rw-r--r-- | arch/arm/mm/cache-v4wb.S | 11 |
1 files changed, 6 insertions, 5 deletions
diff --git a/arch/arm/mm/cache-v4wb.S b/arch/arm/mm/cache-v4wb.S index 2ebc1b3bf856..3dbedf1ec0e7 100644 --- a/arch/arm/mm/cache-v4wb.S +++ b/arch/arm/mm/cache-v4wb.S | |||
@@ -114,15 +114,16 @@ ENTRY(v4wb_flush_user_cache_range) | |||
114 | mov pc, lr | 114 | mov pc, lr |
115 | 115 | ||
116 | /* | 116 | /* |
117 | * flush_kern_dcache_page(void *page) | 117 | * flush_kern_dcache_area(void *addr, size_t size) |
118 | * | 118 | * |
119 | * Ensure no D cache aliasing occurs, either with itself or | 119 | * Ensure no D cache aliasing occurs, either with itself or |
120 | * the I cache | 120 | * the I cache |
121 | * | 121 | * |
122 | * - addr - page aligned address | 122 | * - addr - kernel address |
123 | * - size - region size | ||
123 | */ | 124 | */ |
124 | ENTRY(v4wb_flush_kern_dcache_page) | 125 | ENTRY(v4wb_flush_kern_dcache_area) |
125 | add r1, r0, #PAGE_SZ | 126 | add r1, r0, r1 |
126 | /* fall through */ | 127 | /* fall through */ |
127 | 128 | ||
128 | /* | 129 | /* |
@@ -224,7 +225,7 @@ ENTRY(v4wb_cache_fns) | |||
224 | .long v4wb_flush_user_cache_range | 225 | .long v4wb_flush_user_cache_range |
225 | .long v4wb_coherent_kern_range | 226 | .long v4wb_coherent_kern_range |
226 | .long v4wb_coherent_user_range | 227 | .long v4wb_coherent_user_range |
227 | .long v4wb_flush_kern_dcache_page | 228 | .long v4wb_flush_kern_dcache_area |
228 | .long v4wb_dma_inv_range | 229 | .long v4wb_dma_inv_range |
229 | .long v4wb_dma_clean_range | 230 | .long v4wb_dma_clean_range |
230 | .long v4wb_dma_flush_range | 231 | .long v4wb_dma_flush_range |