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authorAnders Grafström <grfstrm@users.sourceforge.net>2008-10-16 12:37:24 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2008-10-17 08:44:27 -0400
commite4d2a5985af957d2c0da61fb978d0c414b92a562 (patch)
tree0f8adefd6c9d91e1da76c3e833d29e36a3a72623 /arch/arm/mm/cache-v4.S
parent957cf333b5284943c4866e1d0339a105d2762c9c (diff)
[ARM] 5310/1: Fix cache flush functions for ARMv4
ARMv4 (ARM720T) cache flush functions are broken in 2.6.19+ kernels. The issue was introduced by commit f12d0d7c7786af39435ef6ae9defe47fb58f6091 This patch corrects the CPU_CP15 ifdef statements so that they actually do something. Signed-off-by: Anders Grafström <grfstrm@users.sourceforge.net> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mm/cache-v4.S')
-rw-r--r--arch/arm/mm/cache-v4.S6
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/arm/mm/cache-v4.S b/arch/arm/mm/cache-v4.S
index 33926c9fcda6..5786adf10040 100644
--- a/arch/arm/mm/cache-v4.S
+++ b/arch/arm/mm/cache-v4.S
@@ -29,7 +29,7 @@ ENTRY(v4_flush_user_cache_all)
29 * Clean and invalidate the entire cache. 29 * Clean and invalidate the entire cache.
30 */ 30 */
31ENTRY(v4_flush_kern_cache_all) 31ENTRY(v4_flush_kern_cache_all)
32#ifdef CPU_CP15 32#ifdef CONFIG_CPU_CP15
33 mov r0, #0 33 mov r0, #0
34 mcr p15, 0, r0, c7, c7, 0 @ flush ID cache 34 mcr p15, 0, r0, c7, c7, 0 @ flush ID cache
35 mov pc, lr 35 mov pc, lr
@@ -48,7 +48,7 @@ ENTRY(v4_flush_kern_cache_all)
48 * - flags - vma_area_struct flags describing address space 48 * - flags - vma_area_struct flags describing address space
49 */ 49 */
50ENTRY(v4_flush_user_cache_range) 50ENTRY(v4_flush_user_cache_range)
51#ifdef CPU_CP15 51#ifdef CONFIG_CPU_CP15
52 mov ip, #0 52 mov ip, #0
53 mcreq p15, 0, ip, c7, c7, 0 @ flush ID cache 53 mcreq p15, 0, ip, c7, c7, 0 @ flush ID cache
54 mov pc, lr 54 mov pc, lr
@@ -116,7 +116,7 @@ ENTRY(v4_dma_inv_range)
116 * - end - virtual end address 116 * - end - virtual end address
117 */ 117 */
118ENTRY(v4_dma_flush_range) 118ENTRY(v4_dma_flush_range)
119#ifdef CPU_CP15 119#ifdef CONFIG_CPU_CP15
120 mov r0, #0 120 mov r0, #0
121 mcr p15, 0, r0, c7, c7, 0 @ flush ID cache 121 mcr p15, 0, r0, c7, c7, 0 @ flush ID cache
122#endif 122#endif