diff options
author | Russell King <rmk@dyn-67.arm.linux.org.uk> | 2006-09-28 17:20:39 -0400 |
---|---|---|
committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2006-09-28 17:20:39 -0400 |
commit | 250d375d1da45a5e08ab8baf5eaa7eb258afd82b (patch) | |
tree | fb5dc6df00065f11578f837835c6d5a99530b223 /arch/arm/mm/cache-v4.S | |
parent | 84904d0ead0a8c419abd45c7b2ac8d76d50a0d48 (diff) | |
parent | 6afd6fae1d5f7e7129a10c4f3e32018966eeac1c (diff) |
Merge nommu branch
Diffstat (limited to 'arch/arm/mm/cache-v4.S')
-rw-r--r-- | arch/arm/mm/cache-v4.S | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/arch/arm/mm/cache-v4.S b/arch/arm/mm/cache-v4.S index b8ad5d58ebe2..b2908063ed6a 100644 --- a/arch/arm/mm/cache-v4.S +++ b/arch/arm/mm/cache-v4.S | |||
@@ -29,9 +29,13 @@ ENTRY(v4_flush_user_cache_all) | |||
29 | * Clean and invalidate the entire cache. | 29 | * Clean and invalidate the entire cache. |
30 | */ | 30 | */ |
31 | ENTRY(v4_flush_kern_cache_all) | 31 | ENTRY(v4_flush_kern_cache_all) |
32 | #ifdef CPU_CP15 | ||
32 | mov r0, #0 | 33 | mov r0, #0 |
33 | mcr p15, 0, r0, c7, c7, 0 @ flush ID cache | 34 | mcr p15, 0, r0, c7, c7, 0 @ flush ID cache |
34 | mov pc, lr | 35 | mov pc, lr |
36 | #else | ||
37 | /* FALLTHROUGH */ | ||
38 | #endif | ||
35 | 39 | ||
36 | /* | 40 | /* |
37 | * flush_user_cache_range(start, end, flags) | 41 | * flush_user_cache_range(start, end, flags) |
@@ -44,9 +48,13 @@ ENTRY(v4_flush_kern_cache_all) | |||
44 | * - flags - vma_area_struct flags describing address space | 48 | * - flags - vma_area_struct flags describing address space |
45 | */ | 49 | */ |
46 | ENTRY(v4_flush_user_cache_range) | 50 | ENTRY(v4_flush_user_cache_range) |
51 | #ifdef CPU_CP15 | ||
47 | mov ip, #0 | 52 | mov ip, #0 |
48 | mcreq p15, 0, ip, c7, c7, 0 @ flush ID cache | 53 | mcreq p15, 0, ip, c7, c7, 0 @ flush ID cache |
49 | mov pc, lr | 54 | mov pc, lr |
55 | #else | ||
56 | /* FALLTHROUGH */ | ||
57 | #endif | ||
50 | 58 | ||
51 | /* | 59 | /* |
52 | * coherent_kern_range(start, end) | 60 | * coherent_kern_range(start, end) |
@@ -108,8 +116,10 @@ ENTRY(v4_dma_inv_range) | |||
108 | * - end - virtual end address | 116 | * - end - virtual end address |
109 | */ | 117 | */ |
110 | ENTRY(v4_dma_flush_range) | 118 | ENTRY(v4_dma_flush_range) |
119 | #ifdef CPU_CP15 | ||
111 | mov r0, #0 | 120 | mov r0, #0 |
112 | mcr p15, 0, r0, c7, c7, 0 @ flush ID cache | 121 | mcr p15, 0, r0, c7, c7, 0 @ flush ID cache |
122 | #endif | ||
113 | /* FALLTHROUGH */ | 123 | /* FALLTHROUGH */ |
114 | 124 | ||
115 | /* | 125 | /* |