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authorRussell King <rmk+kernel@arm.linux.org.uk>2009-11-26 11:24:19 -0500
committerRussell King <rmk+kernel@arm.linux.org.uk>2010-02-15 10:22:23 -0500
commit702b94bff3c50542a6e4ab9a4f4cef093262fe65 (patch)
tree2ae468b08de2aeb0e65ab3830c40c7a84dbbdb5e /arch/arm/mm/cache-v3.S
parenta9c9147eb9b1dba0ce567a41897c7773b4d1b0bc (diff)
ARM: dma-mapping: remove dmac_clean_range and dmac_inv_range
These are now unused, and so can be removed. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Tested-By: Santosh Shilimkar <santosh.shilimkar@ti.com>
Diffstat (limited to 'arch/arm/mm/cache-v3.S')
-rw-r--r--arch/arm/mm/cache-v3.S29
1 files changed, 1 insertions, 28 deletions
diff --git a/arch/arm/mm/cache-v3.S b/arch/arm/mm/cache-v3.S
index 6df52dc014be..c2ff3c599fee 100644
--- a/arch/arm/mm/cache-v3.S
+++ b/arch/arm/mm/cache-v3.S
@@ -84,20 +84,6 @@ ENTRY(v3_flush_kern_dcache_area)
84 /* FALLTHROUGH */ 84 /* FALLTHROUGH */
85 85
86/* 86/*
87 * dma_inv_range(start, end)
88 *
89 * Invalidate (discard) the specified virtual address range.
90 * May not write back any entries. If 'start' or 'end'
91 * are not cache line aligned, those lines must be written
92 * back.
93 *
94 * - start - virtual start address
95 * - end - virtual end address
96 */
97ENTRY(v3_dma_inv_range)
98 /* FALLTHROUGH */
99
100/*
101 * dma_flush_range(start, end) 87 * dma_flush_range(start, end)
102 * 88 *
103 * Clean and invalidate the specified virtual address range. 89 * Clean and invalidate the specified virtual address range.
@@ -108,17 +94,6 @@ ENTRY(v3_dma_inv_range)
108ENTRY(v3_dma_flush_range) 94ENTRY(v3_dma_flush_range)
109 mov r0, #0 95 mov r0, #0
110 mcr p15, 0, r0, c7, c0, 0 @ flush ID cache 96 mcr p15, 0, r0, c7, c0, 0 @ flush ID cache
111 /* FALLTHROUGH */
112
113/*
114 * dma_clean_range(start, end)
115 *
116 * Clean (write back) the specified virtual address range.
117 *
118 * - start - virtual start address
119 * - end - virtual end address
120 */
121ENTRY(v3_dma_clean_range)
122 mov pc, lr 97 mov pc, lr
123 98
124/* 99/*
@@ -129,7 +104,7 @@ ENTRY(v3_dma_clean_range)
129 */ 104 */
130ENTRY(v3_dma_unmap_area) 105ENTRY(v3_dma_unmap_area)
131 teq r2, #DMA_TO_DEVICE 106 teq r2, #DMA_TO_DEVICE
132 bne v3_dma_inv_range 107 bne v3_dma_flush_range
133 /* FALLTHROUGH */ 108 /* FALLTHROUGH */
134 109
135/* 110/*
@@ -155,7 +130,5 @@ ENTRY(v3_cache_fns)
155 .long v3_flush_kern_dcache_area 130 .long v3_flush_kern_dcache_area
156 .long v3_dma_map_area 131 .long v3_dma_map_area
157 .long v3_dma_unmap_area 132 .long v3_dma_unmap_area
158 .long v3_dma_inv_range
159 .long v3_dma_clean_range
160 .long v3_dma_flush_range 133 .long v3_dma_flush_range
161 .size v3_cache_fns, . - v3_cache_fns 134 .size v3_cache_fns, . - v3_cache_fns