diff options
author | Chao Xie <xiechao.mail@gmail.com> | 2012-07-31 02:13:12 -0400 |
---|---|---|
committer | Haojian Zhuang <haojian.zhuang@gmail.com> | 2012-08-16 04:16:27 -0400 |
commit | 38f2e3772429f29a273a2ed7e95dd7a41f662f06 (patch) | |
tree | 2cf21a73ab581cabc5b03a34464dec7ac1178007 /arch/arm/mm/cache-tauros2.c | |
parent | fa79b8d6a2f38bf2c612acf38787a7fcf60c5db7 (diff) |
ARM: cache: add extra feature enable for tauros2
The extra feature may be used by SOCs are prefetch, burst8,
write buffer coalesce
Signed-off-by: Chao Xie <xiechao.mail@gmail.com>
Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
Diffstat (limited to 'arch/arm/mm/cache-tauros2.c')
-rw-r--r-- | arch/arm/mm/cache-tauros2.c | 44 |
1 files changed, 27 insertions, 17 deletions
diff --git a/arch/arm/mm/cache-tauros2.c b/arch/arm/mm/cache-tauros2.c index 4b787bba2b58..e9f054fc7e87 100644 --- a/arch/arm/mm/cache-tauros2.c +++ b/arch/arm/mm/cache-tauros2.c | |||
@@ -145,21 +145,6 @@ static inline void __init write_extra_features(u32 u) | |||
145 | __asm__("mcr p15, 1, %0, c15, c1, 0" : : "r" (u)); | 145 | __asm__("mcr p15, 1, %0, c15, c1, 0" : : "r" (u)); |
146 | } | 146 | } |
147 | 147 | ||
148 | static void __init disable_l2_prefetch(void) | ||
149 | { | ||
150 | u32 u; | ||
151 | |||
152 | /* | ||
153 | * Read the CPU Extra Features register and verify that the | ||
154 | * Disable L2 Prefetch bit is set. | ||
155 | */ | ||
156 | u = read_extra_features(); | ||
157 | if (!(u & 0x01000000)) { | ||
158 | printk(KERN_INFO "Tauros2: Disabling L2 prefetch.\n"); | ||
159 | write_extra_features(u | 0x01000000); | ||
160 | } | ||
161 | } | ||
162 | |||
163 | static inline int __init cpuid_scheme(void) | 148 | static inline int __init cpuid_scheme(void) |
164 | { | 149 | { |
165 | return !!((processor_id & 0x000f0000) == 0x000f0000); | 150 | return !!((processor_id & 0x000f0000) == 0x000f0000); |
@@ -188,11 +173,36 @@ static inline void __init write_actlr(u32 actlr) | |||
188 | __asm__("mcr p15, 0, %0, c1, c0, 1\n" : : "r" (actlr)); | 173 | __asm__("mcr p15, 0, %0, c1, c0, 1\n" : : "r" (actlr)); |
189 | } | 174 | } |
190 | 175 | ||
191 | void __init tauros2_init(void) | 176 | static void enable_extra_feature(unsigned int features) |
177 | { | ||
178 | u32 u; | ||
179 | |||
180 | u = read_extra_features(); | ||
181 | |||
182 | if (features & CACHE_TAUROS2_PREFETCH_ON) | ||
183 | u &= ~0x01000000; | ||
184 | else | ||
185 | u |= 0x01000000; | ||
186 | printk(KERN_INFO "Tauros2: %s L2 prefetch.\n", | ||
187 | (features & CACHE_TAUROS2_PREFETCH_ON) | ||
188 | ? "Enabling" : "Disabling"); | ||
189 | |||
190 | if (features & CACHE_TAUROS2_LINEFILL_BURST8) | ||
191 | u |= 0x00100000; | ||
192 | else | ||
193 | u &= ~0x00100000; | ||
194 | printk(KERN_INFO "Tauros2: %s line fill burt8.\n", | ||
195 | (features & CACHE_TAUROS2_LINEFILL_BURST8) | ||
196 | ? "Enabling" : "Disabling"); | ||
197 | |||
198 | write_extra_features(u); | ||
199 | } | ||
200 | |||
201 | void __init tauros2_init(unsigned int features) | ||
192 | { | 202 | { |
193 | char *mode = NULL; | 203 | char *mode = NULL; |
194 | 204 | ||
195 | disable_l2_prefetch(); | 205 | enable_extra_feature(features); |
196 | 206 | ||
197 | #ifdef CONFIG_CPU_32v5 | 207 | #ifdef CONFIG_CPU_32v5 |
198 | if ((processor_id & 0xff0f0000) == 0x56050000) { | 208 | if ((processor_id & 0xff0f0000) == 0x56050000) { |