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authorWill Deacon <will.deacon@arm.com>2013-06-12 04:59:59 -0400
committerWill Deacon <will.deacon@arm.com>2013-08-12 07:25:46 -0400
commit9781aa8adbc13b9960b5a3a7353efc57eeb3697d (patch)
tree944dc8fccc55a50233b4f7b68a736020472aeefa /arch/arm/mm/cache-l2x0.c
parent40a5c0b415f080638a744177653aac4527002bbf (diff)
ARM: l2x0: use -st dsb option for ordering writel_relaxed with unlock
writel_relaxed and spin_unlock are both store operations, so we only need to enforce store ordering in the dsb. Signed-off-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to 'arch/arm/mm/cache-l2x0.c')
-rw-r--r--arch/arm/mm/cache-l2x0.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index d70e0aba0c9d..0c3fc276bd30 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -290,7 +290,7 @@ static void l2x0_disable(void)
290 raw_spin_lock_irqsave(&l2x0_lock, flags); 290 raw_spin_lock_irqsave(&l2x0_lock, flags);
291 __l2x0_flush_all(); 291 __l2x0_flush_all();
292 writel_relaxed(0, l2x0_base + L2X0_CTRL); 292 writel_relaxed(0, l2x0_base + L2X0_CTRL);
293 dsb(); 293 dsb(st);
294 raw_spin_unlock_irqrestore(&l2x0_lock, flags); 294 raw_spin_unlock_irqrestore(&l2x0_lock, flags);
295} 295}
296 296