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author | Thomas Gleixner <tglx@linutronix.de> | 2011-03-12 07:22:22 -0500 |
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committer | Thomas Gleixner <tglx@linutronix.de> | 2011-03-12 07:22:28 -0500 |
commit | cfe08bba1e0017d94a8f738a195d3a2b479327e3 (patch) | |
tree | 4546939fd9fbddc978b6eaa0299b03177e9e643b /arch/arm/mm/cache-l2x0.c | |
parent | 58bff947e2d164c7e5cbf7f485e4b3d4884befeb (diff) | |
parent | abb0052289e58140d933b29491f59e4be0a19727 (diff) |
Merge branch 'x86/apic' into x86/irq
Reason: Update to latest genirq code conflicts with pending apic
changes
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Diffstat (limited to 'arch/arm/mm/cache-l2x0.c')
-rw-r--r-- | arch/arm/mm/cache-l2x0.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c index 170c9bb95866..f2ce38e085d2 100644 --- a/arch/arm/mm/cache-l2x0.c +++ b/arch/arm/mm/cache-l2x0.c | |||
@@ -49,7 +49,13 @@ static inline void cache_wait(void __iomem *reg, unsigned long mask) | |||
49 | static inline void cache_sync(void) | 49 | static inline void cache_sync(void) |
50 | { | 50 | { |
51 | void __iomem *base = l2x0_base; | 51 | void __iomem *base = l2x0_base; |
52 | |||
53 | #ifdef CONFIG_ARM_ERRATA_753970 | ||
54 | /* write to an unmmapped register */ | ||
55 | writel_relaxed(0, base + L2X0_DUMMY_REG); | ||
56 | #else | ||
52 | writel_relaxed(0, base + L2X0_CACHE_SYNC); | 57 | writel_relaxed(0, base + L2X0_CACHE_SYNC); |
58 | #endif | ||
53 | cache_wait(base + L2X0_CACHE_SYNC, 1); | 59 | cache_wait(base + L2X0_CACHE_SYNC, 1); |
54 | } | 60 | } |
55 | 61 | ||