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authorRussell King <rmk+kernel@arm.linux.org.uk>2014-03-15 12:47:50 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2014-05-29 19:47:34 -0400
commit37abcdb9194001a0c6ccc5508cd84ea8bd92c29c (patch)
tree2851190136172f7e60d4aaa02410a000895ac6a8 /arch/arm/mm/cache-l2x0.c
parent2b2a87a12d2e0aede29e45911aeb0c520066b0c0 (diff)
ARM: l2c: split out cache unlock code
Split the cache unlock code out of l2x0_unlock(). We want to be able to re-use this functionality later. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mm/cache-l2x0.c')
-rw-r--r--arch/arm/mm/cache-l2x0.c23
1 files changed, 16 insertions, 7 deletions
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index 595c50519e41..a1313d20f205 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -50,6 +50,9 @@ struct l2x0_regs l2x0_saved_regs;
50 50
51static bool of_init = false; 51static bool of_init = false;
52 52
53/*
54 * Common code for all cache controllers.
55 */
53static inline void cache_wait_way(void __iomem *reg, unsigned long mask) 56static inline void cache_wait_way(void __iomem *reg, unsigned long mask)
54{ 57{
55 /* wait for cache operation by line or way to complete */ 58 /* wait for cache operation by line or way to complete */
@@ -67,6 +70,18 @@ static inline void l2c_set_debug(void __iomem *base, unsigned long val)
67 outer_cache.set_debug(val); 70 outer_cache.set_debug(val);
68} 71}
69 72
73static inline void l2c_unlock(void __iomem *base, unsigned num)
74{
75 unsigned i;
76
77 for (i = 0; i < num; i++) {
78 writel_relaxed(0, base + L2X0_LOCKDOWN_WAY_D_BASE +
79 i * L2X0_LOCKDOWN_STRIDE);
80 writel_relaxed(0, base + L2X0_LOCKDOWN_WAY_I_BASE +
81 i * L2X0_LOCKDOWN_STRIDE);
82 }
83}
84
70#ifdef CONFIG_CACHE_PL310 85#ifdef CONFIG_CACHE_PL310
71static inline void cache_wait(void __iomem *reg, unsigned long mask) 86static inline void cache_wait(void __iomem *reg, unsigned long mask)
72{ 87{
@@ -308,7 +323,6 @@ static void l2x0_disable(void)
308static void l2x0_unlock(u32 cache_id) 323static void l2x0_unlock(u32 cache_id)
309{ 324{
310 int lockregs; 325 int lockregs;
311 int i;
312 326
313 switch (cache_id & L2X0_CACHE_ID_PART_MASK) { 327 switch (cache_id & L2X0_CACHE_ID_PART_MASK) {
314 case L2X0_CACHE_ID_PART_L310: 328 case L2X0_CACHE_ID_PART_L310:
@@ -323,12 +337,7 @@ static void l2x0_unlock(u32 cache_id)
323 break; 337 break;
324 } 338 }
325 339
326 for (i = 0; i < lockregs; i++) { 340 l2c_unlock(l2x0_base, lockregs);
327 writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_D_BASE +
328 i * L2X0_LOCKDOWN_STRIDE);
329 writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_I_BASE +
330 i * L2X0_LOCKDOWN_STRIDE);
331 }
332} 341}
333 342
334void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask) 343void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask)