Merge branch 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm

* 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm: (100 commits)
  ARM: Eliminate decompressor -Dstatic= PIC hack
  ARM: 5958/1: ARM: U300: fix inverted clk round rate
  ARM: 5956/1: misplaced parentheses
  ARM: 5955/1: ep93xx: move timer defines into core.c and document
  ARM: 5954/1: ep93xx: move gpio interrupt support to gpio.c
  ARM: 5953/1: ep93xx: fix broken build of clock.c
  ARM: 5952/1: ARM: MM: Add ARM_L1_CACHE_SHIFT_6 for handle inside each ARCH Kconfig
  ARM: 5949/1: NUC900 add gpio virtual memory map
  ARM: 5948/1: Enable timer0 to time4 clock support for nuc910
  ARM: 5940/2: ARM: MMCI: remove custom DBG macro and printk
  ARM: make_coherent(): fix problems with highpte, part 2
  MM: Pass a PTE pointer to update_mmu_cache() rather than the PTE itself
  ARM: 5945/1: ep93xx: include correct irq.h in core.c
  ARM: 5933/1: amba-pl011: support hardware flow control
  ARM: 5930/1: Add PKMAP area description to memory.txt.
  ARM: 5929/1: Add checks to detect overlap of memory regions.
  ARM: 5928/1: Change type of VMALLOC_END to unsigned long.
  ARM: 5927/1: Make delimiters of DMA area globally visibly.
  ARM: 5926/1: Add "Virtual kernel memory..." printout.
  ARM: 5920/1: OMAP4: Enable L2 Cache
  ...

Fix up trivial conflict in arch/arm/mach-mx25/clock.c

1 files changed, 62 insertions, 10 deletions

diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index cb8fc6573b1b..07334632d3e2 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -42,6 +42,57 @@ static inline void cache_sync(void)
         cache_wait(base + L2X0_CACHE_SYNC, 1);
 }
 
+static inline void l2x0_clean_line(unsigned long addr)
+{
+        void __iomem *base = l2x0_base;
+        cache_wait(base + L2X0_CLEAN_LINE_PA, 1);
+        writel(addr, base + L2X0_CLEAN_LINE_PA);
+}
+
+static inline void l2x0_inv_line(unsigned long addr)
+{
+        void __iomem *base = l2x0_base;
+        cache_wait(base + L2X0_INV_LINE_PA, 1);
+        writel(addr, base + L2X0_INV_LINE_PA);
+}
+
+#ifdef CONFIG_PL310_ERRATA_588369
+static void debug_writel(unsigned long val)
+{
+        extern void omap_smc1(u32 fn, u32 arg);
+
+        /*
+         * Texas Instrument secure monitor api to modify the
+         * PL310 Debug Control Register.
+         */
+        omap_smc1(0x100, val);
+}
+
+static inline void l2x0_flush_line(unsigned long addr)
+{
+        void __iomem *base = l2x0_base;
+
+        /* Clean by PA followed by Invalidate by PA */
+        cache_wait(base + L2X0_CLEAN_LINE_PA, 1);
+        writel(addr, base + L2X0_CLEAN_LINE_PA);
+        cache_wait(base + L2X0_INV_LINE_PA, 1);
+        writel(addr, base + L2X0_INV_LINE_PA);
+}
+#else
+
+/* Optimised out for non-errata case */
+static inline void debug_writel(unsigned long val)
+{
+}
+
+static inline void l2x0_flush_line(unsigned long addr)
+{
+        void __iomem *base = l2x0_base;
+        cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1);
+        writel(addr, base + L2X0_CLEAN_INV_LINE_PA);
+}
+#endif
+
 static inline void l2x0_inv_all(void)
 {
         unsigned long flags;
@@ -62,23 +113,24 @@ static void l2x0_inv_range(unsigned long start, unsigned long end)
         spin_lock_irqsave(&l2x0_lock, flags);
         if (start & (CACHE_LINE_SIZE - 1)) {
                 start &= ~(CACHE_LINE_SIZE - 1);
-                cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1);
-                writel(start, base + L2X0_CLEAN_INV_LINE_PA);
+                debug_writel(0x03);
+                l2x0_flush_line(start);
+                debug_writel(0x00);
                 start += CACHE_LINE_SIZE;
         }
 
         if (end & (CACHE_LINE_SIZE - 1)) {
                 end &= ~(CACHE_LINE_SIZE - 1);
-                cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1);
-                writel(end, base + L2X0_CLEAN_INV_LINE_PA);
+                debug_writel(0x03);
+                l2x0_flush_line(end);
+                debug_writel(0x00);
         }
 
         while (start < end) {
                 unsigned long blk_end = start + min(end - start, 4096UL);
 
                 while (start < blk_end) {
-                        cache_wait(base + L2X0_INV_LINE_PA, 1);
-                        writel(start, base + L2X0_INV_LINE_PA);
+                        l2x0_inv_line(start);
                         start += CACHE_LINE_SIZE;
                 }
 
@@ -103,8 +155,7 @@ static void l2x0_clean_range(unsigned long start, unsigned long end)
                 unsigned long blk_end = start + min(end - start, 4096UL);
 
                 while (start < blk_end) {
-                        cache_wait(base + L2X0_CLEAN_LINE_PA, 1);
-                        writel(start, base + L2X0_CLEAN_LINE_PA);
+                        l2x0_clean_line(start);
                         start += CACHE_LINE_SIZE;
                 }
 
@@ -128,11 +179,12 @@ static void l2x0_flush_range(unsigned long start, unsigned long end)
         while (start < end) {
                 unsigned long blk_end = start + min(end - start, 4096UL);
 
+                debug_writel(0x03);
                 while (start < blk_end) {
-                        cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1);
-                        writel(start, base + L2X0_CLEAN_INV_LINE_PA);
+                        l2x0_flush_line(start);
                         start += CACHE_LINE_SIZE;
                 }
+                debug_writel(0x00);
 
                 if (blk_end < end) {
                         spin_unlock_irqrestore(&l2x0_lock, flags);