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authorDan Williams <dan.j.williams@intel.com>2010-05-17 19:30:58 -0400
committerDan Williams <dan.j.williams@intel.com>2010-05-17 19:30:58 -0400
commit0b28330e39bbe0ffee4c56b09fc415fcec595ea3 (patch)
treefcf504879883763557e696eff81427b1ab78f76b /arch/arm/mm/cache-l2x0.c
parent058276303dbc4ed089c1f7dad0871810b1f5ddf1 (diff)
parentcaa20d974c86af496b419eef70010e63b7fab7ac (diff)
Merge branch 'ioat' into dmaengine
Diffstat (limited to 'arch/arm/mm/cache-l2x0.c')
-rw-r--r--arch/arm/mm/cache-l2x0.c10
1 files changed, 10 insertions, 0 deletions
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index 07334632d3e2..21ad68ba22ba 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -93,6 +93,15 @@ static inline void l2x0_flush_line(unsigned long addr)
93} 93}
94#endif 94#endif
95 95
96static void l2x0_cache_sync(void)
97{
98 unsigned long flags;
99
100 spin_lock_irqsave(&l2x0_lock, flags);
101 cache_sync();
102 spin_unlock_irqrestore(&l2x0_lock, flags);
103}
104
96static inline void l2x0_inv_all(void) 105static inline void l2x0_inv_all(void)
97{ 106{
98 unsigned long flags; 107 unsigned long flags;
@@ -225,6 +234,7 @@ void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask)
225 outer_cache.inv_range = l2x0_inv_range; 234 outer_cache.inv_range = l2x0_inv_range;
226 outer_cache.clean_range = l2x0_clean_range; 235 outer_cache.clean_range = l2x0_clean_range;
227 outer_cache.flush_range = l2x0_flush_range; 236 outer_cache.flush_range = l2x0_flush_range;
237 outer_cache.sync = l2x0_cache_sync;
228 238
229 printk(KERN_INFO "L2X0 cache controller enabled\n"); 239 printk(KERN_INFO "L2X0 cache controller enabled\n");
230} 240}