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authorRussell King <rmk+kernel@arm.linux.org.uk>2014-03-15 12:47:49 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2014-05-29 19:47:41 -0400
commit14b882cfa3f9db3430037dca6038e161eda953a1 (patch)
treeeed503cb7e2cd572d1055dec4916e6439372bb04 /arch/arm/mm/cache-l2x0.c
parent83841fe1fb0c4316af89ab85d3528702724a33f4 (diff)
ARM: l2c: add and use L2C revision constants
The revision namespace is specific to the L2 cache part, so don't name these with generic identifiers, use a part specific identifier. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mm/cache-l2x0.c')
-rw-r--r--arch/arm/mm/cache-l2x0.c10
1 files changed, 5 insertions, 5 deletions
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index 29ee7f692801..c39602ef2cdd 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -374,7 +374,7 @@ void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask)
374 /* Unmapped register. */ 374 /* Unmapped register. */
375 sync_reg_offset = L2X0_DUMMY_REG; 375 sync_reg_offset = L2X0_DUMMY_REG;
376#endif 376#endif
377 if ((cache_id & L2X0_CACHE_ID_RTL_MASK) <= L2X0_CACHE_ID_RTL_R3P0) 377 if ((cache_id & L2X0_CACHE_ID_RTL_MASK) <= L310_CACHE_ID_RTL_R3P0)
378 outer_cache.set_debug = pl310_set_debug; 378 outer_cache.set_debug = pl310_set_debug;
379 break; 379 break;
380 case L2X0_CACHE_ID_PART_L210: 380 case L2X0_CACHE_ID_PART_L210:
@@ -768,7 +768,7 @@ static void __init pl310_save(void)
768 l2x0_saved_regs.filter_start = readl_relaxed(l2x0_base + 768 l2x0_saved_regs.filter_start = readl_relaxed(l2x0_base +
769 L2X0_ADDR_FILTER_START); 769 L2X0_ADDR_FILTER_START);
770 770
771 if (l2x0_revision >= L2X0_CACHE_ID_RTL_R2P0) { 771 if (l2x0_revision >= L310_CACHE_ID_RTL_R2P0) {
772 /* 772 /*
773 * From r2p0, there is Prefetch offset/control register 773 * From r2p0, there is Prefetch offset/control register
774 */ 774 */
@@ -777,7 +777,7 @@ static void __init pl310_save(void)
777 /* 777 /*
778 * From r3p0, there is Power control register 778 * From r3p0, there is Power control register
779 */ 779 */
780 if (l2x0_revision >= L2X0_CACHE_ID_RTL_R3P0) 780 if (l2x0_revision >= L310_CACHE_ID_RTL_R3P0)
781 l2x0_saved_regs.pwr_ctrl = readl_relaxed(l2x0_base + 781 l2x0_saved_regs.pwr_ctrl = readl_relaxed(l2x0_base +
782 L2X0_POWER_CTRL); 782 L2X0_POWER_CTRL);
783 } 783 }
@@ -830,10 +830,10 @@ static void pl310_resume(void)
830 l2x0_revision = readl_relaxed(l2x0_base + L2X0_CACHE_ID) & 830 l2x0_revision = readl_relaxed(l2x0_base + L2X0_CACHE_ID) &
831 L2X0_CACHE_ID_RTL_MASK; 831 L2X0_CACHE_ID_RTL_MASK;
832 832
833 if (l2x0_revision >= L2X0_CACHE_ID_RTL_R2P0) { 833 if (l2x0_revision >= L310_CACHE_ID_RTL_R2P0) {
834 writel_relaxed(l2x0_saved_regs.prefetch_ctrl, 834 writel_relaxed(l2x0_saved_regs.prefetch_ctrl,
835 l2x0_base + L2X0_PREFETCH_CTRL); 835 l2x0_base + L2X0_PREFETCH_CTRL);
836 if (l2x0_revision >= L2X0_CACHE_ID_RTL_R3P0) 836 if (l2x0_revision >= L310_CACHE_ID_RTL_R3P0)
837 writel_relaxed(l2x0_saved_regs.pwr_ctrl, 837 writel_relaxed(l2x0_saved_regs.pwr_ctrl,
838 l2x0_base + L2X0_POWER_CTRL); 838 l2x0_base + L2X0_POWER_CTRL);
839 } 839 }