Merge remote branch 'intel/drm-intel-next' of /ssd/git/drm-next into drm-core-next

* 'intel/drm-intel-next' of /ssd/git/drm-next: (230 commits)
  drm/i915: Clear the Ironlake dithering flags when the pipe doesn't want it.
  drm/agp/i915: trim stolen space to 32M
  drm/i915: Unset cursor if out-of-bounds upon mode change (v4)
  drm/i915: Unreference object not handle on creation
  drm/i915: Attempt to uncouple object after catastrophic failure in unbind
  drm/i915: Repeat unbinding during free if interrupted (v6)
  drm/i915: Refactor i915_gem_retire_requests()
  drm/i915: Warn if we run out of FIFO space for a mode
  drm/i915: Round up the watermark entries (v3)
  drm/i915: Typo in (unused) register mask for overlay.
  drm/i915: Check overlay stride errata for i830 and i845
  drm/i915: Validate the mode for eDP by using fixed panel size
  drm/i915: Always use the fixed panel timing for eDP
  drm/i915: Enable panel fitting for eDP
  drm/i915: Add fixed panel mode parsed from EDID for eDP without fixed mode in VBT
  drm/i915/sdvo: Set sync polarity based on actual mode
  drm/i915/hdmi: Set sync polarity based on actual mode
  drm/i915/pch: Set transcoder sync polarity for DP based on actual mode
  drm/i915: Initialize LVDS and eDP outputs before anything else
  drm/i915/dp: Correctly report eDP in the core connector type
  ...

1 files changed, 13 insertions, 13 deletions

diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index df4955885b21..9982eb385c0f 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -32,14 +32,14 @@ static uint32_t l2x0_way_mask;	/* Bitmask of active ways */
 static inline void cache_wait(void __iomem *reg, unsigned long mask)
 {
         /* wait for the operation to complete */
-        while (readl(reg) & mask)
+        while (readl_relaxed(reg) & mask)
                 ;
 }
 
 static inline void cache_sync(void)
 {
         void __iomem *base = l2x0_base;
-        writel(0, base + L2X0_CACHE_SYNC);
+        writel_relaxed(0, base + L2X0_CACHE_SYNC);
         cache_wait(base + L2X0_CACHE_SYNC, 1);
 }
 
@@ -47,14 +47,14 @@ static inline void l2x0_clean_line(unsigned long addr)
 {
         void __iomem *base = l2x0_base;
         cache_wait(base + L2X0_CLEAN_LINE_PA, 1);
-        writel(addr, base + L2X0_CLEAN_LINE_PA);
+        writel_relaxed(addr, base + L2X0_CLEAN_LINE_PA);
 }
 
 static inline void l2x0_inv_line(unsigned long addr)
 {
         void __iomem *base = l2x0_base;
         cache_wait(base + L2X0_INV_LINE_PA, 1);
-        writel(addr, base + L2X0_INV_LINE_PA);
+        writel_relaxed(addr, base + L2X0_INV_LINE_PA);
 }
 
 #ifdef CONFIG_PL310_ERRATA_588369
@@ -75,9 +75,9 @@ static inline void l2x0_flush_line(unsigned long addr)
 
         /* Clean by PA followed by Invalidate by PA */
         cache_wait(base + L2X0_CLEAN_LINE_PA, 1);
-        writel(addr, base + L2X0_CLEAN_LINE_PA);
+        writel_relaxed(addr, base + L2X0_CLEAN_LINE_PA);
         cache_wait(base + L2X0_INV_LINE_PA, 1);
-        writel(addr, base + L2X0_INV_LINE_PA);
+        writel_relaxed(addr, base + L2X0_INV_LINE_PA);
 }
 #else
 
@@ -90,7 +90,7 @@ static inline void l2x0_flush_line(unsigned long addr)
 {
         void __iomem *base = l2x0_base;
         cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1);
-        writel(addr, base + L2X0_CLEAN_INV_LINE_PA);
+        writel_relaxed(addr, base + L2X0_CLEAN_INV_LINE_PA);
 }
 #endif
 
@@ -109,7 +109,7 @@ static inline void l2x0_inv_all(void)
 
         /* invalidate all ways */
         spin_lock_irqsave(&l2x0_lock, flags);
-        writel(l2x0_way_mask, l2x0_base + L2X0_INV_WAY);
+        writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_INV_WAY);
         cache_wait(l2x0_base + L2X0_INV_WAY, l2x0_way_mask);
         cache_sync();
         spin_unlock_irqrestore(&l2x0_lock, flags);
@@ -215,8 +215,8 @@ void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask)
 
         l2x0_base = base;
 
-        cache_id = readl(l2x0_base + L2X0_CACHE_ID);
-        aux = readl(l2x0_base + L2X0_AUX_CTRL);
+        cache_id = readl_relaxed(l2x0_base + L2X0_CACHE_ID);
+        aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
 
         aux &= aux_mask;
         aux |= aux_val;
@@ -248,15 +248,15 @@ void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask)
          * If you are booting from non-secure mode
          * accessing the below registers will fault.
          */
-        if (!(readl(l2x0_base + L2X0_CTRL) & 1)) {
+        if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & 1)) {
 
                 /* l2x0 controller is disabled */
-                writel(aux, l2x0_base + L2X0_AUX_CTRL);
+                writel_relaxed(aux, l2x0_base + L2X0_AUX_CTRL);
 
                 l2x0_inv_all();
 
                 /* enable L2X0 */
-                writel(1, l2x0_base + L2X0_CTRL);
+                writel_relaxed(1, l2x0_base + L2X0_CTRL);
         }
 
         outer_cache.inv_range = l2x0_inv_range;