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| author | Linus Torvalds <torvalds@g5.osdl.org> | 2006-09-28 17:40:39 -0400 |
|---|---|---|
| committer | Linus Torvalds <torvalds@g5.osdl.org> | 2006-09-28 17:40:39 -0400 |
| commit | ebdea46fecae40c4d7effcd33f40918a37a1df4b (patch) | |
| tree | e4312bf7f1f3d184738963a0ec300aa9fdfd55c1 /arch/arm/mm/abort-lv4t.S | |
| parent | fecf3404f4aba6d0edeba31eeb018cbb6326dff2 (diff) | |
| parent | 250d375d1da45a5e08ab8baf5eaa7eb258afd82b (diff) | |
Merge branch 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm
* 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm: (130 commits)
[ARM] 3856/1: Add clocksource for Intel IXP4xx platforms
[ARM] 3855/1: Add generic time support
[ARM] 3873/1: S3C24XX: Add irq_chip names
[ARM] 3872/1: S3C24XX: Apply consistant tabbing to irq_chips
[ARM] 3871/1: S3C24XX: Fix ordering of EINT4..23
[ARM] nommu: confirms the CR_V bit in nommu mode
[ARM] nommu: abort handler fixup for !CPU_CP15_MMU cores.
[ARM] 3870/1: AT91: Start removing static memory mappings
[ARM] 3869/1: AT91: NAND support for DK and KB9202 boards
[ARM] 3868/1: AT91 hardware header update
[ARM] 3867/1: AT91 GPIO update
[ARM] 3866/1: AT91 clock update
[ARM] 3865/1: AT91RM9200 header updates
[ARM] 3862/2: S3C2410 - add basic power management support for AML M5900 series
[ARM] kthread: switch arch/arm/kernel/apm.c
[ARM] Off-by-one in arch/arm/common/icst*
[ARM] 3864/1: Refactore sharpsl_pm
[ARM] 3863/1: Add Locomo SPI Device
[ARM] 3847/2: Convert LOMOMO to use struct device for GPIOs
[ARM] Use CPU_CACHE_* where possible in asm/cacheflush.h
...
Diffstat (limited to 'arch/arm/mm/abort-lv4t.S')
| -rw-r--r-- | arch/arm/mm/abort-lv4t.S | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/arch/arm/mm/abort-lv4t.S b/arch/arm/mm/abort-lv4t.S index db743e510214..9fb7b0e25ea1 100644 --- a/arch/arm/mm/abort-lv4t.S +++ b/arch/arm/mm/abort-lv4t.S | |||
| @@ -19,11 +19,16 @@ | |||
| 19 | */ | 19 | */ |
| 20 | ENTRY(v4t_late_abort) | 20 | ENTRY(v4t_late_abort) |
| 21 | tst r3, #PSR_T_BIT @ check for thumb mode | 21 | tst r3, #PSR_T_BIT @ check for thumb mode |
| 22 | #ifdef CONFIG_CPU_CP15_MMU | ||
| 22 | mrc p15, 0, r1, c5, c0, 0 @ get FSR | 23 | mrc p15, 0, r1, c5, c0, 0 @ get FSR |
| 23 | mrc p15, 0, r0, c6, c0, 0 @ get FAR | 24 | mrc p15, 0, r0, c6, c0, 0 @ get FAR |
| 25 | bic r1, r1, #1 << 11 | 1 << 10 @ clear bits 11 and 10 of FSR | ||
| 26 | #else | ||
| 27 | mov r0, #0 @ clear r0, r1 (no FSR/FAR) | ||
| 28 | mov r1, #0 | ||
| 29 | #endif | ||
| 24 | bne .data_thumb_abort | 30 | bne .data_thumb_abort |
| 25 | ldr r8, [r2] @ read arm instruction | 31 | ldr r8, [r2] @ read arm instruction |
| 26 | bic r1, r1, #1 << 11 | 1 << 10 @ clear bits 11 and 10 of FSR | ||
| 27 | tst r8, #1 << 20 @ L = 1 -> write? | 32 | tst r8, #1 << 20 @ L = 1 -> write? |
| 28 | orreq r1, r1, #1 << 11 @ yes. | 33 | orreq r1, r1, #1 << 11 @ yes. |
| 29 | and r7, r8, #15 << 24 | 34 | and r7, r8, #15 << 24 |