ARM: entry: data abort: tail-call the main data abort handler

Tail-call the main C data abort handler code from the per-CPU helper
code.  Update the comments in the code wrt the new calling and return
register state.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

1 files changed, 5 insertions, 8 deletions

diff --git a/arch/arm/mm/abort-ev5tj.S b/arch/arm/mm/abort-ev5tj.S
index ccfbc937054d..4006b7a61264 100644
--- a/arch/arm/mm/abort-ev5tj.S
+++ b/arch/arm/mm/abort-ev5tj.S
@@ -4,14 +4,11 @@
 /*
  * Function: v5tj_early_abort
  *
- * Params  : r4 = aborted context pc
+ * Params  : r2 = pt_regs
+ *         : r4 = aborted context pc
  *         : r5 = aborted context psr
  *
- * Returns : r0 = address of abort
- *         : r1 = FSR, bit 11 = write
- *         : r2-r8 = corrupted
- *         : r9 = preserved
- *         : sp = pointer to registers
+ * Returns : r4 - r11, r13 preserved
  *
  * Purpose : obtain information about current aborted instruction.
  * Note: we read user space.  This means we might cause a data
@@ -24,10 +21,10 @@ ENTRY(v5tj_early_abort)
         mrc     p15, 0, r0, c6, c0, 0           @ get FAR
         bic     r1, r1, #1 << 11 | 1 << 10      @ clear bits 11 and 10 of FSR
         tst     r5, #PSR_J_BIT                  @ Java?
-        movne   pc, lr
+        bne     do_DataAbort
         do_thumb_abort fsr=r1, pc=r4, psr=r5, tmp=r3
         ldreq   r3, [r4]                        @ read aborted ARM instruction
         do_ldrd_abort tmp=ip, insn=r3
         tst     r3, #1 << 20                    @ L = 0 -> write
         orreq   r1, r1, #1 << 11                @ yes.
-        mov     pc, lr
+        b       do_DataAbort