ARM: entry: data abort: arrange for CPU abort helpers to take pc/psr in r4/r5

Re-jig the CPU abort helpers to take the PC/PSR in r4/r5 rather
than r2/r3.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

1 files changed, 4 insertions, 4 deletions

diff --git a/arch/arm/mm/abort-ev4t.S b/arch/arm/mm/abort-ev4t.S
index 9910123079ce..eaa4ac023959 100644
--- a/arch/arm/mm/abort-ev4t.S
+++ b/arch/arm/mm/abort-ev4t.S
@@ -4,8 +4,8 @@
 /*
  * Function: v4t_early_abort
  *
- * Params  : r2 = address of aborted instruction
- *         : r3 = saved SPSR
+ * Params  : r4 = aborted context pc
+ *         : r5 = aborted context psr
  *
  * Returns : r0 = address of abort
  *         : r1 = FSR, bit 11 = write
@@ -22,8 +22,8 @@
 ENTRY(v4t_early_abort)
         mrc     p15, 0, r1, c5, c0, 0           @ get FSR
         mrc     p15, 0, r0, c6, c0, 0           @ get FAR
-        do_thumb_abort fsr=r1, pc=r2, psr=r3, tmp=r3
-        ldreq   r3, [r2]                        @ read aborted ARM instruction
+        do_thumb_abort fsr=r1, pc=r4, psr=r5, tmp=r3
+        ldreq   r3, [r4]                        @ read aborted ARM instruction
         bic     r1, r1, #1 << 11 | 1 << 10      @ clear bits 11 and 10 of FSR
         tst     r3, #1 << 20                    @ check write
         orreq   r1, r1, #1 << 11