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authorCatalin Marinas <catalin.marinas@arm.com>2008-04-21 13:42:04 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2008-04-24 05:06:45 -0400
commit4a1fd556c1f1fbd6d9d6739efec042324732b697 (patch)
tree0175c078b97e3e74249a07df619280832fa06b37 /arch/arm/mm/Kconfig
parent328d8a012583f0c25f8db25a2e5e63b521201542 (diff)
[ARM] fix 48d7927bdf071d05cf5d15b816cf06b0937cb84f
The proc-*.S files have the _prefetch_abort pointer placed at the end of the processor structure but the cpu-multi32.h defines it in the second position. The patch also fixes the support for XSC3 and the MMU-less CPUs (740, 7tdmi, 940, 946 and 9tdmi). Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mm/Kconfig')
-rw-r--r--arch/arm/mm/Kconfig6
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 746cbb7c8e95..1b8229d9c9d5 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -32,6 +32,7 @@ config CPU_ARM7TDMI
32 depends on !MMU 32 depends on !MMU
33 select CPU_32v4T 33 select CPU_32v4T
34 select CPU_ABRT_LV4T 34 select CPU_ABRT_LV4T
35 select CPU_PABRT_NOIFAR
35 select CPU_CACHE_V4 36 select CPU_CACHE_V4
36 help 37 help
37 A 32-bit RISC microprocessor based on the ARM7 processor core 38 A 32-bit RISC microprocessor based on the ARM7 processor core
@@ -85,6 +86,7 @@ config CPU_ARM740T
85 depends on !MMU 86 depends on !MMU
86 select CPU_32v4T 87 select CPU_32v4T
87 select CPU_ABRT_LV4T 88 select CPU_ABRT_LV4T
89 select CPU_PABRT_NOIFAR
88 select CPU_CACHE_V3 # although the core is v4t 90 select CPU_CACHE_V3 # although the core is v4t
89 select CPU_CP15_MPU 91 select CPU_CP15_MPU
90 help 92 help
@@ -101,6 +103,7 @@ config CPU_ARM9TDMI
101 depends on !MMU 103 depends on !MMU
102 select CPU_32v4T 104 select CPU_32v4T
103 select CPU_ABRT_NOMMU 105 select CPU_ABRT_NOMMU
106 select CPU_PABRT_NOIFAR
104 select CPU_CACHE_V4 107 select CPU_CACHE_V4
105 help 108 help
106 A 32-bit RISC microprocessor based on the ARM9 processor core 109 A 32-bit RISC microprocessor based on the ARM9 processor core
@@ -200,6 +203,7 @@ config CPU_ARM940T
200 depends on !MMU 203 depends on !MMU
201 select CPU_32v4T 204 select CPU_32v4T
202 select CPU_ABRT_NOMMU 205 select CPU_ABRT_NOMMU
206 select CPU_PABRT_NOIFAR
203 select CPU_CACHE_VIVT 207 select CPU_CACHE_VIVT
204 select CPU_CP15_MPU 208 select CPU_CP15_MPU
205 help 209 help
@@ -217,6 +221,7 @@ config CPU_ARM946E
217 depends on !MMU 221 depends on !MMU
218 select CPU_32v5 222 select CPU_32v5
219 select CPU_ABRT_NOMMU 223 select CPU_ABRT_NOMMU
224 select CPU_PABRT_NOIFAR
220 select CPU_CACHE_VIVT 225 select CPU_CACHE_VIVT
221 select CPU_CP15_MPU 226 select CPU_CP15_MPU
222 help 227 help
@@ -351,6 +356,7 @@ config CPU_XSC3
351 default y 356 default y
352 select CPU_32v5 357 select CPU_32v5
353 select CPU_ABRT_EV5T 358 select CPU_ABRT_EV5T
359 select CPU_PABRT_NOIFAR
354 select CPU_CACHE_VIVT 360 select CPU_CACHE_VIVT
355 select CPU_CP15_MMU 361 select CPU_CP15_MMU
356 select CPU_TLB_V4WBI if MMU 362 select CPU_TLB_V4WBI if MMU