ARM: 5791/1: ARM: MM: use 64bytes of L1 cache on plat S5PC1xx

Samsung S5PC1xx SoCs are based on ARM Coretex8, which has 64 bytes of L1
cache line size. Enable proper handling of L1 cache on these SoCs.

Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

1 files changed, 1 insertions, 1 deletions

diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index e993140edd88..9cf7706e0be0 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -777,5 +777,5 @@ config CACHE_XSC3L2
 
 config ARM_L1_CACHE_SHIFT
         int
-        default 6 if ARCH_OMAP3
+        default 6 if ARCH_OMAP3 || ARCH_S5PC1XX
         default 5