Add a prefetch abort handler

This patch adds a prefetch abort handler similar to the data abort one
and renames the latter for consistency. Initial implementation by Paul
Brook with some renaming by Catalin Marinas.

Signed-off-by: Paul Brook <paul@codesourcery.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

1 files changed, 23 insertions, 0 deletions

diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 084fe8de3efe..708ee25b8df4 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -18,6 +18,7 @@ config CPU_ARM610
         select CPU_CP15_MMU
         select CPU_COPY_V3 if MMU
         select CPU_TLB_V3 if MMU
+        select CPU_PABRT_NOIFAR
         help
           The ARM610 is the successor to the ARM3 processor
           and was produced by VLSI Technology Inc.
@@ -49,6 +50,7 @@ config CPU_ARM710
         select CPU_CP15_MMU
         select CPU_COPY_V3 if MMU
         select CPU_TLB_V3 if MMU
+        select CPU_PABRT_NOIFAR
         help
           A 32-bit RISC microprocessor based on the ARM7 processor core
           designed by Advanced RISC Machines Ltd. The ARM710 is the
@@ -64,6 +66,7 @@ config CPU_ARM720T
         default y if ARCH_CLPS711X || ARCH_L7200 || ARCH_CDB89712 || ARCH_H720X
         select CPU_32v4T
         select CPU_ABRT_LV4T
+        select CPU_PABRT_NOIFAR
         select CPU_CACHE_V4
         select CPU_CACHE_VIVT
         select CPU_CP15_MMU
@@ -113,6 +116,7 @@ config CPU_ARM920T
         default y if CPU_S3C2410 || CPU_S3C2440 || CPU_S3C2442 || ARCH_AT91RM9200
         select CPU_32v4T
         select CPU_ABRT_EV4T
+        select CPU_PABRT_NOIFAR
         select CPU_CACHE_V4WT
         select CPU_CACHE_VIVT
         select CPU_CP15_MMU
@@ -135,6 +139,7 @@ config CPU_ARM922T
         default y if ARCH_LH7A40X || ARCH_KS8695
         select CPU_32v4T
         select CPU_ABRT_EV4T
+        select CPU_PABRT_NOIFAR
         select CPU_CACHE_V4WT
         select CPU_CACHE_VIVT
         select CPU_CP15_MMU
@@ -155,6 +160,7 @@ config CPU_ARM925T
         default y if ARCH_OMAP15XX
         select CPU_32v4T
         select CPU_ABRT_EV4T
+        select CPU_PABRT_NOIFAR
         select CPU_CACHE_V4WT
         select CPU_CACHE_VIVT
         select CPU_CP15_MMU
@@ -175,6 +181,7 @@ config CPU_ARM926T
         default y if ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || ARCH_AT91SAM9263 || ARCH_AT91SAM9RL || ARCH_AT91CAP9 || ARCH_NS9XXX || ARCH_DAVINCI
         select CPU_32v5
         select CPU_ABRT_EV5TJ
+        select CPU_PABRT_NOIFAR
         select CPU_CACHE_VIVT
         select CPU_CP15_MMU
         select CPU_COPY_V4WB if MMU
@@ -226,6 +233,7 @@ config CPU_ARM1020
         depends on ARCH_INTEGRATOR
         select CPU_32v5
         select CPU_ABRT_EV4T
+        select CPU_PABRT_NOIFAR
         select CPU_CACHE_V4WT
         select CPU_CACHE_VIVT
         select CPU_CP15_MMU
@@ -244,6 +252,7 @@ config CPU_ARM1020E
         depends on ARCH_INTEGRATOR
         select CPU_32v5
         select CPU_ABRT_EV4T
+        select CPU_PABRT_NOIFAR
         select CPU_CACHE_V4WT
         select CPU_CACHE_VIVT
         select CPU_CP15_MMU
@@ -257,6 +266,7 @@ config CPU_ARM1022
         depends on ARCH_INTEGRATOR
         select CPU_32v5
         select CPU_ABRT_EV4T
+        select CPU_PABRT_NOIFAR
         select CPU_CACHE_VIVT
         select CPU_CP15_MMU
         select CPU_COPY_V4WB if MMU # can probably do better
@@ -275,6 +285,7 @@ config CPU_ARM1026
         depends on ARCH_INTEGRATOR
         select CPU_32v5
         select CPU_ABRT_EV5T # But need Jazelle, but EV5TJ ignores bit 10
+        select CPU_PABRT_NOIFAR
         select CPU_CACHE_VIVT
         select CPU_CP15_MMU
         select CPU_COPY_V4WB if MMU # can probably do better
@@ -293,6 +304,7 @@ config CPU_SA110
         select CPU_32v3 if ARCH_RPC
         select CPU_32v4 if !ARCH_RPC
         select CPU_ABRT_EV4
+        select CPU_PABRT_NOIFAR
         select CPU_CACHE_V4WB
         select CPU_CACHE_VIVT
         select CPU_CP15_MMU
@@ -314,6 +326,7 @@ config CPU_SA1100
         default y
         select CPU_32v4
         select CPU_ABRT_EV4
+        select CPU_PABRT_NOIFAR
         select CPU_CACHE_V4WB
         select CPU_CACHE_VIVT
         select CPU_CP15_MMU
@@ -326,6 +339,7 @@ config CPU_XSCALE
         default y
         select CPU_32v5
         select CPU_ABRT_EV5T
+        select CPU_PABRT_NOIFAR
         select CPU_CACHE_VIVT
         select CPU_CP15_MMU
         select CPU_TLB_V4WBI if MMU
@@ -349,6 +363,7 @@ config CPU_FEROCEON
         default y
         select CPU_32v5
         select CPU_ABRT_EV5T
+        select CPU_PABRT_NOIFAR
         select CPU_CACHE_VIVT
         select CPU_CP15_MMU
         select CPU_COPY_V4WB if MMU
@@ -371,6 +386,7 @@ config CPU_V6
         default y if ARCH_MSM7X00A
         select CPU_32v6
         select CPU_ABRT_EV6
+        select CPU_PABRT_NOIFAR
         select CPU_CACHE_V6
         select CPU_CACHE_VIPT
         select CPU_CP15_MMU
@@ -397,6 +413,7 @@ config CPU_V7
         select CPU_32v6K
         select CPU_32v7
         select CPU_ABRT_EV7
+        select CPU_PABRT_IFAR
         select CPU_CACHE_V7
         select CPU_CACHE_VIPT
         select CPU_CP15_MMU
@@ -458,6 +475,12 @@ config CPU_ABRT_EV6
 config CPU_ABRT_EV7
         bool
 
+config CPU_PABRT_IFAR
+        bool
+
+config CPU_PABRT_NOIFAR
+        bool
+
 # The cache model
 config CPU_CACHE_V3
         bool