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authorNick Bowler <nbowler@elliptictech.com>2012-11-05 16:45:49 -0500
committerMichal Simek <michal.simek@xilinx.com>2012-11-07 07:48:43 -0500
commitaaf5e0be79e37d5a8509f09852788fa6a82522b2 (patch)
tree0a836f40209121408cf83e74d629239c20ac16ca /arch/arm/mach-zynq
parent78d6785db13572f22d287d8c1739ceb4edf54bdc (diff)
ARM: zynq: Allow UART1 to be used as DEBUG_LL console.
The main UART on the Xilinx ZC702 board is UART1, located at address e0001000. Add a Kconfig option to select this device as the low-level debugging port. This allows the really early boot printouts to reach the USB serial adaptor on this board. For consistency's sake, add a choice entry for UART0 even though it is the the default if UART1 is not selected. Signed-off-by: Nick Bowler <nbowler@elliptictech.com> Tested-by: Josh Cartwright <josh.cartwright@ni.com> Acked-by: Michal Simek <michal.simek@xilinx.com>
Diffstat (limited to 'arch/arm/mach-zynq')
-rw-r--r--arch/arm/mach-zynq/common.c6
-rw-r--r--arch/arm/mach-zynq/include/mach/zynq_soc.h16
2 files changed, 14 insertions, 8 deletions
diff --git a/arch/arm/mach-zynq/common.c b/arch/arm/mach-zynq/common.c
index 6f058258b491..f0eef848c0d0 100644
--- a/arch/arm/mach-zynq/common.c
+++ b/arch/arm/mach-zynq/common.c
@@ -85,9 +85,9 @@ static struct map_desc io_desc[] __initdata = {
85 85
86#ifdef CONFIG_DEBUG_LL 86#ifdef CONFIG_DEBUG_LL
87 { 87 {
88 .virtual = UART0_VIRT, 88 .virtual = LL_UART_VADDR,
89 .pfn = __phys_to_pfn(UART0_PHYS), 89 .pfn = __phys_to_pfn(LL_UART_PADDR),
90 .length = UART0_SIZE, 90 .length = UART_SIZE,
91 .type = MT_DEVICE, 91 .type = MT_DEVICE,
92 }, 92 },
93#endif 93#endif
diff --git a/arch/arm/mach-zynq/include/mach/zynq_soc.h b/arch/arm/mach-zynq/include/mach/zynq_soc.h
index 1b8bf0ecbcb0..5ebbd8e6eeee 100644
--- a/arch/arm/mach-zynq/include/mach/zynq_soc.h
+++ b/arch/arm/mach-zynq/include/mach/zynq_soc.h
@@ -25,8 +25,9 @@
25 * address that is known to work. 25 * address that is known to work.
26 */ 26 */
27#define UART0_PHYS 0xE0000000 27#define UART0_PHYS 0xE0000000
28#define UART0_SIZE SZ_4K 28#define UART1_PHYS 0xE0001000
29#define UART0_VIRT 0xF0001000 29#define UART_SIZE SZ_4K
30#define UART_VIRT 0xF0001000
30 31
31#define TTC0_PHYS 0xF8001000 32#define TTC0_PHYS 0xF8001000
32#define TTC0_SIZE SZ_4K 33#define TTC0_SIZE SZ_4K
@@ -36,12 +37,17 @@
36#define SCU_PERIPH_SIZE SZ_8K 37#define SCU_PERIPH_SIZE SZ_8K
37#define SCU_PERIPH_VIRT (TTC0_VIRT - SCU_PERIPH_SIZE) 38#define SCU_PERIPH_VIRT (TTC0_VIRT - SCU_PERIPH_SIZE)
38 39
40#if IS_ENABLED(CONFIG_DEBUG_ZYNQ_UART1)
41# define LL_UART_PADDR UART1_PHYS
42#else
43# define LL_UART_PADDR UART0_PHYS
44#endif
45
46#define LL_UART_VADDR UART_VIRT
47
39/* The following are intended for the devices that are mapped early */ 48/* The following are intended for the devices that are mapped early */
40 49
41#define TTC0_BASE IOMEM(TTC0_VIRT) 50#define TTC0_BASE IOMEM(TTC0_VIRT)
42#define SCU_PERIPH_BASE IOMEM(SCU_PERIPH_VIRT) 51#define SCU_PERIPH_BASE IOMEM(SCU_PERIPH_VIRT)
43 52
44#define LL_UART_PADDR UART0_PHYS
45#define LL_UART_VADDR UART0_VIRT
46
47#endif 53#endif