diff options
author | Wang Qiang <rurality.linux@gmail.com> | 2010-03-10 18:21:47 -0500 |
---|---|---|
committer | Linus Torvalds <torvalds@linux-foundation.org> | 2010-03-12 18:52:34 -0500 |
commit | 8661970875d7d27e4de233d357327fffdb4a5e3d (patch) | |
tree | 7b8cb8c11bc5e66da62cccf8fd77201415183353 /arch/arm/mach-w90x900 | |
parent | 91d4e0a4c889e3e8078c26542b8f5a322b87adf4 (diff) |
NUC900 LCD Controller Driver
An LCD controller driver for nuc900s. The Linux LOGO is just fine and the
FB-Test application was ok, too.
Signed-off-by: Wang Qiang <rurality.linux@gmail.com>
Cc: Wang Zongshun <mcuos.com@gmail.com>
Cc: Russell King <rmk@arm.linux.org.uk>
Cc: Krzysztof Helt <krzysztof.h1@poczta.fm>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Diffstat (limited to 'arch/arm/mach-w90x900')
-rw-r--r-- | arch/arm/mach-w90x900/cpu.h | 1 | ||||
-rw-r--r-- | arch/arm/mach-w90x900/dev.c | 42 | ||||
-rw-r--r-- | arch/arm/mach-w90x900/include/mach/fb.h | 83 | ||||
-rw-r--r-- | arch/arm/mach-w90x900/include/mach/regs-ldm.h | 253 | ||||
-rw-r--r-- | arch/arm/mach-w90x900/mach-nuc950evb.c | 47 | ||||
-rw-r--r-- | arch/arm/mach-w90x900/nuc950.c | 4 |
6 files changed, 430 insertions, 0 deletions
diff --git a/arch/arm/mach-w90x900/cpu.h b/arch/arm/mach-w90x900/cpu.h index 4d58ba164e25..f8730b60bd76 100644 --- a/arch/arm/mach-w90x900/cpu.h +++ b/arch/arm/mach-w90x900/cpu.h | |||
@@ -57,3 +57,4 @@ extern struct platform_device nuc900_device_fmi; | |||
57 | extern struct platform_device nuc900_device_kpi; | 57 | extern struct platform_device nuc900_device_kpi; |
58 | extern struct platform_device nuc900_device_rtc; | 58 | extern struct platform_device nuc900_device_rtc; |
59 | extern struct platform_device nuc900_device_ts; | 59 | extern struct platform_device nuc900_device_ts; |
60 | extern struct platform_device nuc900_device_lcd; | ||
diff --git a/arch/arm/mach-w90x900/dev.c b/arch/arm/mach-w90x900/dev.c index ec711f4b4019..48876122df91 100644 --- a/arch/arm/mach-w90x900/dev.c +++ b/arch/arm/mach-w90x900/dev.c | |||
@@ -34,6 +34,7 @@ | |||
34 | #include <mach/regs-serial.h> | 34 | #include <mach/regs-serial.h> |
35 | #include <mach/nuc900_spi.h> | 35 | #include <mach/nuc900_spi.h> |
36 | #include <mach/map.h> | 36 | #include <mach/map.h> |
37 | #include <mach/fb.h> | ||
37 | 38 | ||
38 | #include "cpu.h" | 39 | #include "cpu.h" |
39 | 40 | ||
@@ -380,6 +381,47 @@ struct platform_device nuc900_device_kpi = { | |||
380 | .resource = nuc900_kpi_resource, | 381 | .resource = nuc900_kpi_resource, |
381 | }; | 382 | }; |
382 | 383 | ||
384 | #ifdef CONFIG_FB_NUC900 | ||
385 | |||
386 | static struct resource nuc900_lcd_resource[] = { | ||
387 | [0] = { | ||
388 | .start = W90X900_PA_LCD, | ||
389 | .end = W90X900_PA_LCD + W90X900_SZ_LCD - 1, | ||
390 | .flags = IORESOURCE_MEM, | ||
391 | }, | ||
392 | [1] = { | ||
393 | .start = IRQ_LCD, | ||
394 | .end = IRQ_LCD, | ||
395 | .flags = IORESOURCE_IRQ, | ||
396 | } | ||
397 | }; | ||
398 | |||
399 | static u64 nuc900_device_lcd_dmamask = -1; | ||
400 | struct platform_device nuc900_device_lcd = { | ||
401 | .name = "nuc900-lcd", | ||
402 | .id = -1, | ||
403 | .num_resources = ARRAY_SIZE(nuc900_lcd_resource), | ||
404 | .resource = nuc900_lcd_resource, | ||
405 | .dev = { | ||
406 | .dma_mask = &nuc900_device_lcd_dmamask, | ||
407 | .coherent_dma_mask = -1, | ||
408 | } | ||
409 | }; | ||
410 | |||
411 | void nuc900_fb_set_platdata(struct nuc900fb_mach_info *pd) | ||
412 | { | ||
413 | struct nuc900fb_mach_info *npd; | ||
414 | |||
415 | npd = kmalloc(sizeof(*npd), GFP_KERNEL); | ||
416 | if (npd) { | ||
417 | memcpy(npd, pd, sizeof(*npd)); | ||
418 | nuc900_device_lcd.dev.platform_data = npd; | ||
419 | } else { | ||
420 | printk(KERN_ERR "no memory for LCD platform data\n"); | ||
421 | } | ||
422 | } | ||
423 | #endif | ||
424 | |||
383 | /*Here should be your evb resourse,such as LCD*/ | 425 | /*Here should be your evb resourse,such as LCD*/ |
384 | 426 | ||
385 | static struct platform_device *nuc900_public_dev[] __initdata = { | 427 | static struct platform_device *nuc900_public_dev[] __initdata = { |
diff --git a/arch/arm/mach-w90x900/include/mach/fb.h b/arch/arm/mach-w90x900/include/mach/fb.h new file mode 100644 index 000000000000..cec5ece765ed --- /dev/null +++ b/arch/arm/mach-w90x900/include/mach/fb.h | |||
@@ -0,0 +1,83 @@ | |||
1 | /* linux/include/asm/arch-nuc900/fb.h | ||
2 | * | ||
3 | * Copyright (c) 2008 Nuvoton technology corporation | ||
4 | * All rights reserved. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License as published by | ||
8 | * the Free Software Foundation; either version 2 of the License, or | ||
9 | * (at your option) any later version. | ||
10 | * | ||
11 | * Changelog: | ||
12 | * | ||
13 | * 2008/08/26 vincen.zswan modify this file for LCD. | ||
14 | */ | ||
15 | |||
16 | #ifndef __ASM_ARM_FB_H | ||
17 | #define __ASM_ARM_FB_H | ||
18 | |||
19 | |||
20 | |||
21 | /* LCD Controller Hardware Desc */ | ||
22 | struct nuc900fb_hw { | ||
23 | unsigned int lcd_dccs; | ||
24 | unsigned int lcd_device_ctrl; | ||
25 | unsigned int lcd_mpulcd_cmd; | ||
26 | unsigned int lcd_int_cs; | ||
27 | unsigned int lcd_crtc_size; | ||
28 | unsigned int lcd_crtc_dend; | ||
29 | unsigned int lcd_crtc_hr; | ||
30 | unsigned int lcd_crtc_hsync; | ||
31 | unsigned int lcd_crtc_vr; | ||
32 | unsigned int lcd_va_baddr0; | ||
33 | unsigned int lcd_va_baddr1; | ||
34 | unsigned int lcd_va_fbctrl; | ||
35 | unsigned int lcd_va_scale; | ||
36 | unsigned int lcd_va_test; | ||
37 | unsigned int lcd_va_win; | ||
38 | unsigned int lcd_va_stuff; | ||
39 | }; | ||
40 | |||
41 | /* LCD Display Description */ | ||
42 | struct nuc900fb_display { | ||
43 | /* LCD Image type */ | ||
44 | unsigned type; | ||
45 | |||
46 | /* LCD Screen Size */ | ||
47 | unsigned short width; | ||
48 | unsigned short height; | ||
49 | |||
50 | /* LCD Screen Info */ | ||
51 | unsigned short xres; | ||
52 | unsigned short yres; | ||
53 | unsigned short bpp; | ||
54 | |||
55 | unsigned long pixclock; | ||
56 | unsigned short left_margin; | ||
57 | unsigned short right_margin; | ||
58 | unsigned short hsync_len; | ||
59 | unsigned short upper_margin; | ||
60 | unsigned short lower_margin; | ||
61 | unsigned short vsync_len; | ||
62 | |||
63 | /* hardware special register value */ | ||
64 | unsigned int dccs; | ||
65 | unsigned int devctl; | ||
66 | unsigned int fbctrl; | ||
67 | unsigned int scale; | ||
68 | }; | ||
69 | |||
70 | struct nuc900fb_mach_info { | ||
71 | struct nuc900fb_display *displays; | ||
72 | unsigned num_displays; | ||
73 | unsigned default_display; | ||
74 | /* GPIO Setting Info */ | ||
75 | unsigned gpio_dir; | ||
76 | unsigned gpio_dir_mask; | ||
77 | unsigned gpio_data; | ||
78 | unsigned gpio_data_mask; | ||
79 | }; | ||
80 | |||
81 | extern void __init nuc900_fb_set_platdata(struct nuc900fb_mach_info *); | ||
82 | |||
83 | #endif /* __ASM_ARM_FB_H */ | ||
diff --git a/arch/arm/mach-w90x900/include/mach/regs-ldm.h b/arch/arm/mach-w90x900/include/mach/regs-ldm.h new file mode 100644 index 000000000000..e9d480a5b232 --- /dev/null +++ b/arch/arm/mach-w90x900/include/mach/regs-ldm.h | |||
@@ -0,0 +1,253 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-w90x900/include/mach/regs-serial.h | ||
3 | * | ||
4 | * Copyright (c) 2009 Nuvoton technology corporation | ||
5 | * All rights reserved. | ||
6 | * | ||
7 | * This program is free software; you can redistribute it and/or modify | ||
8 | * it under the terms of the GNU General Public License as published by | ||
9 | * the Free Software Foundation; either version 2 of the License, or | ||
10 | * (at your option) any later version. | ||
11 | * | ||
12 | * Description: | ||
13 | * Nuvoton Display, LCM Register list | ||
14 | * Author: Wang Qiang (rurality.linux@gmail.com) 2009/12/11 | ||
15 | * | ||
16 | */ | ||
17 | |||
18 | |||
19 | #ifndef __ASM_ARM_W90X900_REGS_LDM_H | ||
20 | #define __ASM_ARM_W90X900_REGS_LDM_H | ||
21 | |||
22 | #include <mach/map.h> | ||
23 | |||
24 | /* Display Controller Control/Status Register */ | ||
25 | #define REG_LCM_DCCS (0x00) | ||
26 | |||
27 | #define LCM_DCCS_ENG_RST (1 << 0) | ||
28 | #define LCM_DCCS_VA_EN (1 << 1) | ||
29 | #define LCM_DCCS_OSD_EN (1 << 2) | ||
30 | #define LCM_DCCS_DISP_OUT_EN (1 << 3) | ||
31 | #define LCM_DCCS_DISP_INT_EN (1 << 4) | ||
32 | #define LCM_DCCS_CMD_ON (1 << 5) | ||
33 | #define LCM_DCCS_FIELD_INTR (1 << 6) | ||
34 | #define LCM_DCCS_SINGLE (1 << 7) | ||
35 | |||
36 | enum LCM_DCCS_VA_SRC { | ||
37 | LCM_DCCS_VA_SRC_YUV422 = (0 << 8), | ||
38 | LCM_DCCS_VA_SRC_YCBCR422 = (1 << 8), | ||
39 | LCM_DCCS_VA_SRC_RGB888 = (2 << 8), | ||
40 | LCM_DCCS_VA_SRC_RGB666 = (3 << 8), | ||
41 | LCM_DCCS_VA_SRC_RGB565 = (4 << 8), | ||
42 | LCM_DCCS_VA_SRC_RGB444LOW = (5 << 8), | ||
43 | LCM_DCCS_VA_SRC_RGB444HIGH = (7 << 8) | ||
44 | }; | ||
45 | |||
46 | |||
47 | /* Display Device Control Register */ | ||
48 | #define REG_LCM_DEV_CTRL (0x04) | ||
49 | |||
50 | enum LCM_DEV_CTRL_SWAP_YCbCr { | ||
51 | LCM_DEV_CTRL_SWAP_UYVY = (0 << 1), | ||
52 | LCM_DEV_CTRL_SWAP_YUYV = (1 << 1), | ||
53 | LCM_DEV_CTRL_SWAP_VYUY = (2 << 1), | ||
54 | LCM_DEV_CTRL_SWAP_YVYU = (3 << 1) | ||
55 | }; | ||
56 | |||
57 | enum LCM_DEV_CTRL_RGB_SHIFT { | ||
58 | LCM_DEV_CTRL_RGB_SHIFT_NOT = (0 << 3), | ||
59 | LCM_DEV_CTRL_RGB_SHIFT_ONECYCLE = (1 << 3), | ||
60 | LCM_DEV_CTRL_RGB_SHIFT_TWOCYCLE = (2 << 3), | ||
61 | LCM_DEV_CTRL_RGB_SHIFT_NOT_DEF = (3 << 3) | ||
62 | }; | ||
63 | |||
64 | enum LCM_DEV_CTRL_DEVICE { | ||
65 | LCM_DEV_CTRL_DEVICE_YUV422 = (0 << 5), | ||
66 | LCM_DEV_CTRL_DEVICE_YUV444 = (1 << 5), | ||
67 | LCM_DEV_CTRL_DEVICE_UNIPAC = (4 << 5), | ||
68 | LCM_DEV_CTRL_DEVICE_SEIKO_EPSON = (5 << 5), | ||
69 | LCM_DEV_CTRL_DEVICE_HIGH_COLOR = (6 << 5), | ||
70 | LCM_DEV_CTRL_DEVICE_MPU = (7 << 5) | ||
71 | }; | ||
72 | |||
73 | #define LCM_DEV_CTRL_LCD_DDA (8) | ||
74 | #define LCM_DEV_CTRL_YUV2CCIR (16) | ||
75 | |||
76 | enum LCM_DEV_CTRL_LCD_SEL { | ||
77 | LCM_DEV_CTRL_LCD_SEL_RGB_GBR = (0 << 17), | ||
78 | LCM_DEV_CTRL_LCD_SEL_BGR_RBG = (1 << 17), | ||
79 | LCM_DEV_CTRL_LCD_SEL_GBR_RGB = (2 << 17), | ||
80 | LCM_DEV_CTRL_LCD_SEL_RBG_BGR = (3 << 17) | ||
81 | }; | ||
82 | |||
83 | enum LCM_DEV_CTRL_FAL_D { | ||
84 | LCM_DEV_CTRL_FAL_D_FALLING = (0 << 19), | ||
85 | LCM_DEV_CTRL_FAL_D_RISING = (1 << 19), | ||
86 | }; | ||
87 | |||
88 | enum LCM_DEV_CTRL_H_POL { | ||
89 | LCM_DEV_CTRL_H_POL_LOW = (0 << 20), | ||
90 | LCM_DEV_CTRL_H_POL_HIGH = (1 << 20), | ||
91 | }; | ||
92 | |||
93 | enum LCM_DEV_CTRL_V_POL { | ||
94 | LCM_DEV_CTRL_V_POL_LOW = (0 << 21), | ||
95 | LCM_DEV_CTRL_V_POL_HIGH = (1 << 21), | ||
96 | }; | ||
97 | |||
98 | enum LCM_DEV_CTRL_VR_LACE { | ||
99 | LCM_DEV_CTRL_VR_LACE_NINTERLACE = (0 << 22), | ||
100 | LCM_DEV_CTRL_VR_LACE_INTERLACE = (1 << 22), | ||
101 | }; | ||
102 | |||
103 | enum LCM_DEV_CTRL_LACE { | ||
104 | LCM_DEV_CTRL_LACE_NINTERLACE = (0 << 23), | ||
105 | LCM_DEV_CTRL_LACE_INTERLACE = (1 << 23), | ||
106 | }; | ||
107 | |||
108 | enum LCM_DEV_CTRL_RGB_SCALE { | ||
109 | LCM_DEV_CTRL_RGB_SCALE_4096 = (0 << 24), | ||
110 | LCM_DEV_CTRL_RGB_SCALE_65536 = (1 << 24), | ||
111 | LCM_DEV_CTRL_RGB_SCALE_262144 = (2 << 24), | ||
112 | LCM_DEV_CTRL_RGB_SCALE_16777216 = (3 << 24), | ||
113 | }; | ||
114 | |||
115 | enum LCM_DEV_CTRL_DBWORD { | ||
116 | LCM_DEV_CTRL_DBWORD_HALFWORD = (0 << 26), | ||
117 | LCM_DEV_CTRL_DBWORD_FULLWORD = (1 << 26), | ||
118 | }; | ||
119 | |||
120 | enum LCM_DEV_CTRL_MPU68 { | ||
121 | LCM_DEV_CTRL_MPU68_80_SERIES = (0 << 27), | ||
122 | LCM_DEV_CTRL_MPU68_68_SERIES = (1 << 27), | ||
123 | }; | ||
124 | |||
125 | enum LCM_DEV_CTRL_DE_POL { | ||
126 | LCM_DEV_CTRL_DE_POL_HIGH = (0 << 28), | ||
127 | LCM_DEV_CTRL_DE_POL_LOW = (1 << 28), | ||
128 | }; | ||
129 | |||
130 | #define LCM_DEV_CTRL_CMD16 (29) | ||
131 | #define LCM_DEV_CTRL_CM16t18 (30) | ||
132 | #define LCM_DEV_CTRL_CMD_LOW (31) | ||
133 | |||
134 | /* MPU-Interface LCD Write Command */ | ||
135 | #define REG_LCM_MPU_CMD (0x08) | ||
136 | |||
137 | /* Interrupt Control/Status Register */ | ||
138 | #define REG_LCM_INT_CS (0x0c) | ||
139 | #define LCM_INT_CS_DISP_F_EN (1 << 0) | ||
140 | #define LCM_INT_CS_UNDERRUN_EN (1 << 1) | ||
141 | #define LCM_INT_CS_BUS_ERROR_INT (1 << 28) | ||
142 | #define LCM_INT_CS_UNDERRUN_INT (1 << 29) | ||
143 | #define LCM_INT_CS_DISP_F_STATUS (1 << 30) | ||
144 | #define LCM_INT_CS_DISP_F_INT (1 << 31) | ||
145 | |||
146 | /* CRTC Display Size Control Register */ | ||
147 | #define REG_LCM_CRTC_SIZE (0x10) | ||
148 | #define LCM_CRTC_SIZE_VTTVAL(x) ((x) << 16) | ||
149 | #define LCM_CRTC_SIZE_HTTVAL(x) ((x) << 0) | ||
150 | |||
151 | /* CRTC Display Enable End */ | ||
152 | #define REG_LCM_CRTC_DEND (0x14) | ||
153 | #define LCM_CRTC_DEND_VDENDVAL(x) ((x) << 16) | ||
154 | #define LCM_CRTC_DEND_HDENDVAL(x) ((x) << 0) | ||
155 | |||
156 | /* CRTC Internal Horizontal Retrace Control Register */ | ||
157 | #define REG_LCM_CRTC_HR (0x18) | ||
158 | #define LCM_CRTC_HR_EVAL(x) ((x) << 16) | ||
159 | #define LCM_CRTC_HR_SVAL(x) ((x) << 0) | ||
160 | |||
161 | /* CRTC Horizontal Sync Control Register */ | ||
162 | #define REG_LCM_CRTC_HSYNC (0x1C) | ||
163 | #define LCM_CRTC_HSYNC_SHIFTVAL(x) ((x) << 30) | ||
164 | #define LCM_CRTC_HSYNC_EVAL(x) ((x) << 16) | ||
165 | #define LCM_CRTC_HSYNC_SVAL(x) ((x) << 0) | ||
166 | |||
167 | /* CRTC Internal Vertical Retrace Control Register */ | ||
168 | #define REG_LCM_CRTC_VR (0x20) | ||
169 | #define LCM_CRTC_VR_EVAL(x) ((x) << 16) | ||
170 | #define LCM_CRTC_VR_SVAL(x) ((x) << 0) | ||
171 | |||
172 | /* Video Stream Frame Buffer-0 Starting Address */ | ||
173 | #define REG_LCM_VA_BADDR0 (0x24) | ||
174 | |||
175 | /* Video Stream Frame Buffer-1 Starting Address */ | ||
176 | #define REG_LCM_VA_BADDR1 (0x28) | ||
177 | |||
178 | /* Video Stream Frame Buffer Control Register */ | ||
179 | #define REG_LCM_VA_FBCTRL (0x2C) | ||
180 | #define LCM_VA_FBCTRL_IO_REGION_HALF (1 << 28) | ||
181 | #define LCM_VA_FBCTRL_FIELD_DUAL (1 << 29) | ||
182 | #define LCM_VA_FBCTRL_START_BUF (1 << 30) | ||
183 | #define LCM_VA_FBCTRL_DB_EN (1 << 31) | ||
184 | |||
185 | /* Video Stream Scaling Control Register */ | ||
186 | #define REG_LCM_VA_SCALE (0x30) | ||
187 | #define LCM_VA_SCALE_XCOPY_INTERPOLATION (0 << 15) | ||
188 | #define LCM_VA_SCALE_XCOPY_DUPLICATION (1 << 15) | ||
189 | |||
190 | /* Image Stream Active Window Coordinates */ | ||
191 | #define REG_LCM_VA_WIN (0x38) | ||
192 | |||
193 | /* Image Stream Stuff Pixel */ | ||
194 | #define REG_LCM_VA_STUFF (0x3C) | ||
195 | |||
196 | /* OSD Window Starting Coordinates */ | ||
197 | #define REG_LCM_OSD_WINS (0x40) | ||
198 | |||
199 | /* OSD Window Ending Coordinates */ | ||
200 | #define REG_LCM_OSD_WINE (0x44) | ||
201 | |||
202 | /* OSD Stream Frame Buffer Starting Address */ | ||
203 | #define REG_LCM_OSD_BADDR (0x48) | ||
204 | |||
205 | /* OSD Stream Frame Buffer Control Register */ | ||
206 | #define REG_LCM_OSD_FBCTRL (0x4c) | ||
207 | |||
208 | /* OSD Overlay Control Register */ | ||
209 | #define REG_LCM_OSD_OVERLAY (0x50) | ||
210 | |||
211 | /* OSD Overlay Color-Key Pattern Register */ | ||
212 | #define REG_LCM_OSD_CKEY (0x54) | ||
213 | |||
214 | /* OSD Overlay Color-Key Mask Register */ | ||
215 | #define REG_LCM_OSD_CMASK (0x58) | ||
216 | |||
217 | /* OSD Window Skip1 Register */ | ||
218 | #define REG_LCM_OSD_SKIP1 (0x5C) | ||
219 | |||
220 | /* OSD Window Skip2 Register */ | ||
221 | #define REG_LCM_OSD_SKIP2 (0x60) | ||
222 | |||
223 | /* OSD horizontal up scaling control register */ | ||
224 | #define REG_LCM_OSD_SCALE (0x64) | ||
225 | |||
226 | /* MPU Vsync control register */ | ||
227 | #define REG_LCM_MPU_VSYNC (0x68) | ||
228 | |||
229 | /* Hardware cursor control Register */ | ||
230 | #define REG_LCM_HC_CTRL (0x6C) | ||
231 | |||
232 | /* Hardware cursot tip point potison on va picture */ | ||
233 | #define REG_LCM_HC_POS (0x70) | ||
234 | |||
235 | /* Hardware Cursor Window Buffer Control Register */ | ||
236 | #define REG_LCM_HC_WBCTRL (0x74) | ||
237 | |||
238 | /* Hardware cursor memory base address register */ | ||
239 | #define REG_LCM_HC_BADDR (0x78) | ||
240 | |||
241 | /* Hardware cursor color ram register mapped to bpp = 0 */ | ||
242 | #define REG_LCM_HC_COLOR0 (0x7C) | ||
243 | |||
244 | /* Hardware cursor color ram register mapped to bpp = 1 */ | ||
245 | #define REG_LCM_HC_COLOR1 (0x80) | ||
246 | |||
247 | /* Hardware cursor color ram register mapped to bpp = 2 */ | ||
248 | #define REG_LCM_HC_COLOR2 (0x84) | ||
249 | |||
250 | /* Hardware cursor color ram register mapped to bpp = 3 */ | ||
251 | #define REG_LCM_HC_COLOR3 (0x88) | ||
252 | |||
253 | #endif /* __ASM_ARM_W90X900_REGS_LDM_H */ | ||
diff --git a/arch/arm/mach-w90x900/mach-nuc950evb.c b/arch/arm/mach-w90x900/mach-nuc950evb.c index cef903bcccd1..b3edc3cccf52 100644 --- a/arch/arm/mach-w90x900/mach-nuc950evb.c +++ b/arch/arm/mach-w90x900/mach-nuc950evb.c | |||
@@ -10,6 +10,8 @@ | |||
10 | * This program is free software; you can redistribute it and/or | 10 | * This program is free software; you can redistribute it and/or |
11 | * modify it under the terms of the GNU General Public License as | 11 | * modify it under the terms of the GNU General Public License as |
12 | * published by the Free Software Foundation;version 2 of the License. | 12 | * published by the Free Software Foundation;version 2 of the License. |
13 | * history: | ||
14 | * Wang Qiang (rurality.linux@gmail.com) add LCD support | ||
13 | * | 15 | * |
14 | */ | 16 | */ |
15 | 17 | ||
@@ -18,9 +20,51 @@ | |||
18 | #include <asm/mach/map.h> | 20 | #include <asm/mach/map.h> |
19 | #include <asm/mach-types.h> | 21 | #include <asm/mach-types.h> |
20 | #include <mach/map.h> | 22 | #include <mach/map.h> |
23 | #include <mach/regs-ldm.h> | ||
24 | #include <mach/fb.h> | ||
21 | 25 | ||
22 | #include "nuc950.h" | 26 | #include "nuc950.h" |
23 | 27 | ||
28 | #ifdef CONFIG_FB_NUC900 | ||
29 | /* LCD Controller */ | ||
30 | static struct nuc900fb_display __initdata nuc950_lcd_info[] = { | ||
31 | /* Giantplus Technology GPM1040A0 320x240 Color TFT LCD */ | ||
32 | [0] = { | ||
33 | .type = LCM_DCCS_VA_SRC_RGB565, | ||
34 | .width = 320, | ||
35 | .height = 240, | ||
36 | .xres = 320, | ||
37 | .yres = 240, | ||
38 | .bpp = 16, | ||
39 | .pixclock = 200000, | ||
40 | .left_margin = 34, | ||
41 | .right_margin = 54, | ||
42 | .hsync_len = 10, | ||
43 | .upper_margin = 18, | ||
44 | .lower_margin = 4, | ||
45 | .vsync_len = 1, | ||
46 | .dccs = 0x8e00041a, | ||
47 | .devctl = 0x060800c0, | ||
48 | .fbctrl = 0x00a000a0, | ||
49 | .scale = 0x04000400, | ||
50 | }, | ||
51 | }; | ||
52 | |||
53 | static struct nuc900fb_mach_info nuc950_fb_info __initdata = { | ||
54 | #if defined(CONFIG_GPM1040A0_320X240) | ||
55 | .displays = &nuc950_lcd_info[0], | ||
56 | #else | ||
57 | .displays = nuc950_lcd_info, | ||
58 | #endif | ||
59 | .num_displays = ARRAY_SIZE(nuc950_lcd_info), | ||
60 | .default_display = 0, | ||
61 | .gpio_dir = 0x00000004, | ||
62 | .gpio_dir_mask = 0xFFFFFFFD, | ||
63 | .gpio_data = 0x00000004, | ||
64 | .gpio_data_mask = 0xFFFFFFFD, | ||
65 | }; | ||
66 | #endif | ||
67 | |||
24 | static void __init nuc950evb_map_io(void) | 68 | static void __init nuc950evb_map_io(void) |
25 | { | 69 | { |
26 | nuc950_map_io(); | 70 | nuc950_map_io(); |
@@ -30,6 +74,9 @@ static void __init nuc950evb_map_io(void) | |||
30 | static void __init nuc950evb_init(void) | 74 | static void __init nuc950evb_init(void) |
31 | { | 75 | { |
32 | nuc950_board_init(); | 76 | nuc950_board_init(); |
77 | #ifdef CONFIG_FB_NUC900 | ||
78 | nuc900_fb_set_platdata(&nuc950_fb_info); | ||
79 | #endif | ||
33 | } | 80 | } |
34 | 81 | ||
35 | MACHINE_START(W90P950EVB, "W90P950EVB") | 82 | MACHINE_START(W90P950EVB, "W90P950EVB") |
diff --git a/arch/arm/mach-w90x900/nuc950.c b/arch/arm/mach-w90x900/nuc950.c index 149508116d18..4d1f1ab044c4 100644 --- a/arch/arm/mach-w90x900/nuc950.c +++ b/arch/arm/mach-w90x900/nuc950.c | |||
@@ -18,6 +18,7 @@ | |||
18 | #include <linux/platform_device.h> | 18 | #include <linux/platform_device.h> |
19 | #include <asm/mach/map.h> | 19 | #include <asm/mach/map.h> |
20 | #include <mach/hardware.h> | 20 | #include <mach/hardware.h> |
21 | |||
21 | #include "cpu.h" | 22 | #include "cpu.h" |
22 | 23 | ||
23 | /* define specific CPU platform device */ | 24 | /* define specific CPU platform device */ |
@@ -25,6 +26,9 @@ | |||
25 | static struct platform_device *nuc950_dev[] __initdata = { | 26 | static struct platform_device *nuc950_dev[] __initdata = { |
26 | &nuc900_device_kpi, | 27 | &nuc900_device_kpi, |
27 | &nuc900_device_fmi, | 28 | &nuc900_device_fmi, |
29 | #ifdef CONFIG_FB_NUC900 | ||
30 | &nuc900_device_lcd, | ||
31 | #endif | ||
28 | }; | 32 | }; |
29 | 33 | ||
30 | /* define specific CPU platform io map */ | 34 | /* define specific CPU platform io map */ |