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authorPawel Moll <pawel.moll@arm.com>2011-12-09 13:47:39 -0500
committerPawel Moll <pawel.moll@arm.com>2012-02-24 04:18:20 -0500
commit6a3719562b69ffdfc36e829e19b35fda6ab19ca6 (patch)
tree0eb75a57e5f7b54d51d14c315f15cbc1433e2ee7 /arch/arm/mach-vexpress/include
parent8deed1786a6479d0ccda51226582920ab1d6976c (diff)
ARM: vexpress: Motherboard RS1 memory map support
This patch adds support for RS1 memory map based Versatile Express motherboard. Signed-off-by: Pawel Moll <pawel.moll@arm.com>
Diffstat (limited to 'arch/arm/mach-vexpress/include')
-rw-r--r--arch/arm/mach-vexpress/include/mach/debug-macro.S30
-rw-r--r--arch/arm/mach-vexpress/include/mach/uncompress.h22
2 files changed, 47 insertions, 5 deletions
diff --git a/arch/arm/mach-vexpress/include/mach/debug-macro.S b/arch/arm/mach-vexpress/include/mach/debug-macro.S
index fd9e6c7ea49f..fa8224794e0b 100644
--- a/arch/arm/mach-vexpress/include/mach/debug-macro.S
+++ b/arch/arm/mach-vexpress/include/mach/debug-macro.S
@@ -10,12 +10,34 @@
10 * published by the Free Software Foundation. 10 * published by the Free Software Foundation.
11 */ 11 */
12 12
13#define DEBUG_LL_UART_OFFSET 0x00009000 13#define DEBUG_LL_PHYS_BASE 0x10000000
14#define DEBUG_LL_UART_OFFSET 0x00009000
15
16#define DEBUG_LL_PHYS_BASE_RS1 0x1c000000
17#define DEBUG_LL_UART_OFFSET_RS1 0x00090000
18
19#define DEBUG_LL_VIRT_BASE 0xf8000000
14 20
15 .macro addruart,rp,rv,tmp 21 .macro addruart,rp,rv,tmp
16 mov \rp, #DEBUG_LL_UART_OFFSET 22
17 orr \rv, \rp, #0xf8000000 @ virtual base 23 @ Make an educated guess regarding the memory map:
18 orr \rp, \rp, #0x10000000 @ physical base 24 @ - the original A9 core tile, which has MPCore peripherals
25 @ located at 0x1e000000, should use UART at 0x10009000
26 @ - all other (RS1 complaint) tiles use UART mapped
27 @ at 0x1c090000
28 mrc p15, 4, \tmp, c15, c0, 0
29 cmp \tmp, #0x1e000000
30
31 @ Original memory map
32 moveq \rp, #DEBUG_LL_UART_OFFSET
33 orreq \rv, \rp, #DEBUG_LL_VIRT_BASE
34 orreq \rp, \rp, #DEBUG_LL_PHYS_BASE
35
36 @ RS1 memory map
37 movne \rp, #DEBUG_LL_UART_OFFSET_RS1
38 orrne \rv, \rp, #DEBUG_LL_VIRT_BASE
39 orrne \rp, \rp, #DEBUG_LL_PHYS_BASE_RS1
40
19 .endm 41 .endm
20 42
21#include <asm/hardware/debug-pl01x.S> 43#include <asm/hardware/debug-pl01x.S>
diff --git a/arch/arm/mach-vexpress/include/mach/uncompress.h b/arch/arm/mach-vexpress/include/mach/uncompress.h
index 7972c5748d0e..7dab5596b868 100644
--- a/arch/arm/mach-vexpress/include/mach/uncompress.h
+++ b/arch/arm/mach-vexpress/include/mach/uncompress.h
@@ -22,7 +22,27 @@
22#define AMBA_UART_CR(base) (*(volatile unsigned char *)((base) + 0x30)) 22#define AMBA_UART_CR(base) (*(volatile unsigned char *)((base) + 0x30))
23#define AMBA_UART_FR(base) (*(volatile unsigned char *)((base) + 0x18)) 23#define AMBA_UART_FR(base) (*(volatile unsigned char *)((base) + 0x18))
24 24
25#define get_uart_base() (0x10000000 + 0x00009000) 25#define UART_BASE 0x10009000
26#define UART_BASE_RS1 0x1c090000
27
28static unsigned long get_uart_base(void)
29{
30 unsigned long mpcore_periph;
31
32 /*
33 * Make an educated guess regarding the memory map:
34 * - the original A9 core tile, which has MPCore peripherals
35 * located at 0x1e000000, should use UART at 0x10009000
36 * - all other (RS1 complaint) tiles use UART mapped
37 * at 0x1c090000
38 */
39 asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (mpcore_periph));
40
41 if (mpcore_periph == 0x1e000000)
42 return UART_BASE;
43 else
44 return UART_BASE_RS1;
45}
26 46
27/* 47/*
28 * This does not append a newline 48 * This does not append a newline