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author | Olof Johansson <olof@lixom.net> | 2013-01-14 13:20:02 -0500 |
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committer | Olof Johansson <olof@lixom.net> | 2013-01-14 13:20:02 -0500 |
commit | 8d84981e395850aab31c3f2ca7e2738e03f671d7 (patch) | |
tree | 933425fddb23d28be802277471df3fe3f6c2711d /arch/arm/mach-versatile | |
parent | 00c82d64405631967dca3890a9ce80ab35d04cc7 (diff) | |
parent | 77cc982f6a3b33a5aa058ad3b20cda8866db2948 (diff) |
Merge branch 'clocksource/cleanup' into next/cleanup
Clockevent cleanup series from Shawn Guo.
Resolved move/change conflict in mach-pxa/time.c due to the sys_timer
cleanup.
* clocksource/cleanup:
clocksource: use clockevents_config_and_register() where possible
ARM: use clockevents_config_and_register() where possible
clockevents: export clockevents_config_and_register for module use
+ sync to Linux 3.8-rc3
Signed-off-by: Olof Johansson <olof@lixom.net>
Conflicts:
arch/arm/mach-pxa/time.c
Diffstat (limited to 'arch/arm/mach-versatile')
-rw-r--r-- | arch/arm/mach-versatile/include/mach/irqs.h | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/arm/mach-versatile/include/mach/irqs.h b/arch/arm/mach-versatile/include/mach/irqs.h index bf44c61bd1f6..0fd771ca617b 100644 --- a/arch/arm/mach-versatile/include/mach/irqs.h +++ b/arch/arm/mach-versatile/include/mach/irqs.h | |||
@@ -25,7 +25,7 @@ | |||
25 | * IRQ interrupts definitions are the same as the INT definitions | 25 | * IRQ interrupts definitions are the same as the INT definitions |
26 | * held within platform.h | 26 | * held within platform.h |
27 | */ | 27 | */ |
28 | #define IRQ_VIC_START 0 | 28 | #define IRQ_VIC_START 32 |
29 | #define IRQ_WDOGINT (IRQ_VIC_START + INT_WDOGINT) | 29 | #define IRQ_WDOGINT (IRQ_VIC_START + INT_WDOGINT) |
30 | #define IRQ_SOFTINT (IRQ_VIC_START + INT_SOFTINT) | 30 | #define IRQ_SOFTINT (IRQ_VIC_START + INT_SOFTINT) |
31 | #define IRQ_COMMRx (IRQ_VIC_START + INT_COMMRx) | 31 | #define IRQ_COMMRx (IRQ_VIC_START + INT_COMMRx) |
@@ -100,7 +100,7 @@ | |||
100 | /* | 100 | /* |
101 | * Secondary interrupt controller | 101 | * Secondary interrupt controller |
102 | */ | 102 | */ |
103 | #define IRQ_SIC_START 32 | 103 | #define IRQ_SIC_START 64 |
104 | #define IRQ_SIC_MMCI0B (IRQ_SIC_START + SIC_INT_MMCI0B) | 104 | #define IRQ_SIC_MMCI0B (IRQ_SIC_START + SIC_INT_MMCI0B) |
105 | #define IRQ_SIC_MMCI1B (IRQ_SIC_START + SIC_INT_MMCI1B) | 105 | #define IRQ_SIC_MMCI1B (IRQ_SIC_START + SIC_INT_MMCI1B) |
106 | #define IRQ_SIC_KMI0 (IRQ_SIC_START + SIC_INT_KMI0) | 106 | #define IRQ_SIC_KMI0 (IRQ_SIC_START + SIC_INT_KMI0) |
@@ -120,7 +120,7 @@ | |||
120 | #define IRQ_SIC_PCI1 (IRQ_SIC_START + SIC_INT_PCI1) | 120 | #define IRQ_SIC_PCI1 (IRQ_SIC_START + SIC_INT_PCI1) |
121 | #define IRQ_SIC_PCI2 (IRQ_SIC_START + SIC_INT_PCI2) | 121 | #define IRQ_SIC_PCI2 (IRQ_SIC_START + SIC_INT_PCI2) |
122 | #define IRQ_SIC_PCI3 (IRQ_SIC_START + SIC_INT_PCI3) | 122 | #define IRQ_SIC_PCI3 (IRQ_SIC_START + SIC_INT_PCI3) |
123 | #define IRQ_SIC_END 63 | 123 | #define IRQ_SIC_END 95 |
124 | 124 | ||
125 | #define IRQ_GPIO0_START (IRQ_SIC_END + 1) | 125 | #define IRQ_GPIO0_START (IRQ_SIC_END + 1) |
126 | #define IRQ_GPIO0_END (IRQ_GPIO0_START + 31) | 126 | #define IRQ_GPIO0_END (IRQ_GPIO0_START + 31) |